High-Level Synthesis of High-Performance VLSI Processors for Intelligent Integrated System

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Real-world applications need to achieve very quick response for dynamically changing real-world environment. As broad typical examples of the real-world applications, highly-safe systems, robot systems and multimedia systems are considered, and High-level synthesis for their VLSI processors are studied.An optimization problem such that an objective function corresponding to a certain physical factor is discussed under physical constraints in the high-level synthesis. Our approach for the high-level synthesis starts from concrete applications. They are a stereo vision VLSI processor, a collision detection VLSI processor and a path-planning VLSI processor. First, we considered a VLSI-oriented algorithm for each application. Then, optimal structure of arithmetic and logic blocks are derived from the view points of performances and chip areas. The major results are shown below:1. To design high performance VLSI processors in deep-submicron age, it is required to find the architecture such … More that there is no effect on interconnection delay in parallel data transfer between memories and arithmetic modules. For the high-speed and efficient parallel data transfer, an optimal allocation method is developed, and it is applied to design of a stereo vision VLSI processor. The evaluation shows that the performance is greatly increased over the conventional architecture.2. As a collision detection VLSI processor, we proposed a VLSI-oriented algorithm based on hierarchically iteration of coordinate transformation and matching operation. It is confirmed by implementation of the chip that Read-only content addressable memory and bit-serial pipeline architecture make the performance of the VLSI processor very high.3. As an intelligent robot which works autonomously in unknown environment, we proposed a fast path planning algorithm to find a feasible collision-free path. One of the most promising configuration is selected according to a distance between every point in free space and the nearest obstacle. The configuration selection keeps a robot as far away as possible from obstacles, and reduces the number of configurations for collision detection. Moreover, a highly-parallel processor based on logic-in-memory architecture and redundancy of processing elements is proposed to overcome a transfer bottleneck between memory and processing elements. Less