High-Level Synthesis of High-Performance VLSI Processors for Intelligent Integrated System

智能集成系统高性能VLSI处理器的高水平综合

• 批准号: 09450162
• 负责人: KAMEYAMA Michitaka
• 金额: $ 4.35万
• 依托单位: TOHOKU UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1997
• 资助国家: 日本
• 起止时间: 1997 至 1999
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-09450162/
• 关键词: Intelligent Integrated Systems for Real-World Applications; High-Level Synthesis; Scheduling; Allocation; Logic-In-Memory Architecture; Spacially Parallel Structure; Interconnection Network; ロジックインメモリアーキテクチャ; 並列構造VLSIプロセッサ; 演算遅れ時間最小化; 並列データ供給

Real-world applications need to achieve very quick response for dynamically changing real-world environment. As broad typical examples of the real-world applications, highly-safe systems, robot systems and multimedia systems are considered, and High-level synthesis for their VLSI processors are studied.An optimization problem such that an objective function corresponding to a certain physical factor is discussed under physical constraints in the high-level synthesis. Our approach for the high-level synthesis starts from concrete applications. They are a stereo vision VLSI processor, a collision detection VLSI processor and a path-planning VLSI processor. First, we considered a VLSI-oriented algorithm for each application. Then, optimal structure of arithmetic and logic blocks are derived from the view points of performances and chip areas. The major results are shown below:1. To design high performance VLSI processors in deep-submicron age, it is required to find the architecture such … More that there is no effect on interconnection delay in parallel data transfer between memories and arithmetic modules. For the high-speed and efficient parallel data transfer, an optimal allocation method is developed, and it is applied to design of a stereo vision VLSI processor. The evaluation shows that the performance is greatly increased over the conventional architecture.2. As a collision detection VLSI processor, we proposed a VLSI-oriented algorithm based on hierarchically iteration of coordinate transformation and matching operation. It is confirmed by implementation of the chip that Read-only content addressable memory and bit-serial pipeline architecture make the performance of the VLSI processor very high.3. As an intelligent robot which works autonomously in unknown environment, we proposed a fast path planning algorithm to find a feasible collision-free path. One of the most promising configuration is selected according to a distance between every point in free space and the nearest obstacle. The configuration selection keeps a robot as far away as possible from obstacles, and reduces the number of configurations for collision detection. Moreover, a highly-parallel processor based on logic-in-memory architecture and redundancy of processing elements is proposed to overcome a transfer bottleneck between memory and processing elements. Less

现实世界的应用程序需要实现对动态变化的现实世界环境的快速响应。作为实际应用的广泛典型例子，本文以高安全系统、机器人系统和多媒体系统为研究对象，研究了它们的VLSI处理器的高阶综合问题，讨论了高阶综合中的一个优化问题，即目标函数对应于某个物理因子，且具有物理约束。我们的高层次综合方法从具体应用开始。它们分别是立体视觉处理器、碰撞检测处理器和路径规划处理器。首先，我们考虑了一个面向VLSI的算法为每个应用程序。然后，从性能和芯片面积的角度出发，推导出算术和逻辑块的最佳结构。主要研究结果如下：1.为了设计深亚微米时代的高性能VLSI处理器，需要找到这样的体系结构 ...更多信息 在存储器和算术模块之间的并行数据传输中对互连延迟没有影响。为了实现高速高效的并行数据传输，提出了一种最优分配方法，并将其应用于立体视觉处理器的设计中。测试结果表明，与传统的体系结构相比，该体系结构的性能有了很大的提高.作为一种面向VLSI的碰撞检测处理器，我们提出了一种基于坐标变换和匹配操作分层迭代的碰撞检测算法。通过芯片的实现证实了只读内容寻址存储器和位串行流水线结构使VLSI处理器具有很高的性能.针对智能机器人在未知环境中自主工作的问题，提出了一种快速路径规划算法，根据自由空间中各点与最近障碍物的距离，选择最有希望的路径。配置选择使机器人尽可能远离障碍物，并减少碰撞检测的配置数量。此外，提出了一种基于存储器中逻辑结构和处理单元冗余的高并行处理器，以克服存储器和处理单元之间的传输瓶颈。少

项目成果

Masanori Hariyama: "Collision Detection VLSI Processor for Intelligent Vehicles Using a Hierarchically-Content-Addressable Memory"IEICE Trans.Electron. E82-C. 1722-1729 (1999)

Masanori Hariyama：“使用分层内容可寻址存储器的智能车辆碰撞检测 VLSI 处理器”IEICE Trans.Electron。

Masanori Hariyama: "Collision Detection VLSI Processor for Intelligent Vehicles Based on a Hierarchical"IEEE Conference on Intelligent Transportation Systems. (1997)

Masanori Hariyama：“基于分层的智能车辆碰撞检测 VLSI 处理器”IEEE 智能交通系统会议。

亀山充隆,張山昌論: "知能集積システム用VLSIプロセッサの展望"計測自動制御学会学術講演会. 204A-1. (1999)

Mitsutaka Kameyama、Masaharu Hariyama：“智能集成系统的 VLSI 处理器的前景”仪器与控制工程师协会学术会议 204A-1。

張山昌論,李 昇桓,亀山充隆: "高性能ステレオビジョンVLSIプロセッサのアーキテクチャ"日本ロボット学会学術講演会. 1B11. (1999)

张昌三、李承焕、龟山光隆：“高性能立体视觉VLSI处理器的架构”日本机器人学会学术会议1B11。

M.Hariyama and M.kameyama: "Collision Detection VLSI Processor for Intelligent Vehicles Based on a Hierarchical Obstacle Repreesentation" Proc.of the IEEE Conference on Intelligent Transportation Systems. (1997)

M.Hariyama 和 M.kameyama：“基于分层障碍物表示的智能车辆碰撞检测 VLSI 处理器”，IEEE 智能交通系统会议论文集。