Development of Comprehensive Set of LSI CAD Benchmarks

我们已经开发了一套全面的基准，用于对LSI CAD工具进行定量评估。基准测试集以多个抽象级别描述同一电路，因此我们可以自由设置任何类型的基准测试。已经为基准集开发了一套标准的过程无关库。KUE-CHIP2被选为综合基准集的第一个候选者。我们的成果总结如下：1.标准库集的开发我们开发了一套标准的工艺无关库，其形式为CMOS型标准单元库。该图书馆集旨在用于全面的基准，也用于公共领域免费图书馆的研究和教育用途。标准库不是一组库，而是一组库生成工具，可以根据多个工艺参数自动生成特定于工艺的库。布局生成采用符号布局方法。采用一种新的分析方法分析了时延和功耗特性，并考虑了信号转换过程中的短路电流。2.综合基准测试集的开发作为综合基准测试集的第一个例子，我们选择了KUE-CHIP2，这是一款为教育用途而开发的8位微处理器。KUE-CHIP2的VHDL语言描述已经开发出来，并通过一组用于功能验证的测试图样进行了验证，该测试图样与其原始的UDL/I模型一起提供。3.综合基准集的评估KUE-CHIP2基准已经通过使用标准库执行逻辑综合直到自动布局来进行评估。通过使用Synopsis(逻辑综合)和Alliance(自动布局)的Design Compiler对其进行了评估。

We have developed a comprehensive set of benchmarks for quantitative evaluation of LSI CAD tools. The benchmark set describes the same circuit in several levels of abstraction so that we can set up any type of benchmarks freely. A standard set of process independent libraries has been developed for the benchmark set. KUE-CHIP2 is selected for the first candidate of the comprehensive set of benchmarks.Our achivements are summarized as follows.1.The development of standard set of librariesWe have developed a standard set of process independent libraries in a form of CMOS standard cell libraries. The library set is intended to use in comprehensive benchmarks, and also for public domain free libraries for research and educational use. The standard library is not a single set of libraries but a set of library generation tools that automatically produce process specific libraries from several process parameters. Symbolic layout method is used for layout generation. Delay and power dissipation characteristics are analzed by a new analytical method that considers short circuit currents during signal transition. The standard libraries are verified by simulation and also by a test chip.2.Development of a comprehensive set of benchmarksAs the first example of the comprehensive benchmark set, we have selected KUE-CHIP2 which is a 8-bit micro processor developed for educational use. VHDL description of KUE-CHIP2 has been developed and verified by a set of test patterns for functional verification which is supplied with its original UDL/I model.3.Evaluation of a comprehensive set of benchmarksThe KUE-CHIP2 benchmark has been evaluated by performing logic synthesis down to automatic layout with the standard libraries. It is successfully evaluated using Design Compiler of Synopsis (logic synthesis) and Alliance (automatic layout).