Optimization of detailed design for UDSM (ultra deep submicron) integrated circuits

研究了超深亚微米集成电路的优化设计方法。特别地，我们开发了一种门级优化方法，结合版图设计（我们称之为“详细设计”）及其相关技术，在详细设计中，精确的延迟和功耗估计是必要的。我们已经开发了一种准解析方法的延迟和功耗估计CMOS门驱动CRC π负载。估计延迟的误差平均在3%左右，而计算速度比电路模拟快1000倍。详细设计优化的目标是基于单元设计的ASIC。在这种情况下，单元库的性能直接影响到所设计ASIC的性能，我们开发了一个针对目标设计的性能优化的标准单元库生成系统，对于标准单元库的性能，详细设计优化的方法，我们已经在输入重新排序和门尺寸。功耗，以及延迟，优化这些方法。我们关注的是小故障所消耗的功率。考虑到在优化过程中的毛刺减少，我们已经成功地减少功耗进一步从最小尺寸的电路，具有最低的容性负载。

We have studied design optimization methods for UDSM integrated circuits. In particular, we have developed a gate-level optimization method combined with layout design(we call this "detailed design") and its related techniques.In the detailed design, accurate delay and power estimation are necessary. We have developed an quasi-analytical method for delay and power estimation of CMOS gates driving a CRC pi load. The error of the estimated delay is around 3% in average while the calculation speed is 1000 times faster than circuit simulation.The target of the detailed design optimization is a cell-base designed ASIC.In this case, the performance of the cell library directly affects the performance of the designed ASIC.We have developed a generation system of a standard cell library with optimized performance for a target design.As for the methods for detailed design optimization, we have worked on input reordering and gate sizing. Power dissipation, as well as delay, is optimized by these methods. We have focused on the power dissipated by glitches. Considering glitch reduction in the optimization process, we have succeeded to reduce power dissipation further from the minimum sized circuit that has the lowest capacitive load.