Optimization of detailed design for UDSM (ultra deep submicron) integrated circuits

研究了超深亚微米集成电路的设计优化方法。特别是，我们提出了一种与版图设计相结合的门级优化方法(我们称之为详细设计)及其相关技术。在详细设计中，需要准确的延迟和功耗估计。我们发展了一种准解析方法来估计驱动CRC pi负载的CMOS门的延迟和功率。详细设计优化的目标是基于单元的ASIC，单元库的性能直接影响到ASIC的性能。针对目标设计，我们开发了一个具有优化性能的标准单元库生成系统。对于详细设计优化的方法，我们进行了输入重排序和栅极大小的优化。通过这些方法优化了功耗和延迟。我们把重点放在了故障导致的功率消耗上。在优化过程中考虑到毛刺的减少，我们成功地从具有最低电容负载的最小尺寸电路进一步降低了功耗。

We have studied design optimization methods for UDSM integrated circuits. In particular, we have developed a gate-level optimization method combined with layout design(we call this "detailed design") and its related techniques.In the detailed design, accurate delay and power estimation are necessary. We have developed an quasi-analytical method for delay and power estimation of CMOS gates driving a CRC pi load. The error of the estimated delay is around 3% in average while the calculation speed is 1000 times faster than circuit simulation.The target of the detailed design optimization is a cell-base designed ASIC.In this case, the performance of the cell library directly affects the performance of the designed ASIC.We have developed a generation system of a standard cell library with optimized performance for a target design.As for the methods for detailed design optimization, we have worked on input reordering and gate sizing. Power dissipation, as well as delay, is optimized by these methods. We have focused on the power dissipated by glitches. Considering glitch reduction in the optimization process, we have succeeded to reduce power dissipation further from the minimum sized circuit that has the lowest capacitive load.