Simultaneous Circuit and Layout Design Method for Analog LSIs under Performance Constraints

性能约束下模拟LSI的同步电路和布局设计方法

• 批准号: 06680317
• 负责人: ONODERA Hidetoshi
• 金额: $ 1.41万
• 依托单位: KYOTO UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for General Scientific Research (C)
• 财政年份: 1994
• 资助国家: 日本
• 起止时间: 1994 至 1995
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-06680317/
• 关键词: Analog Circuit; Analog Layout; Optimization; Layout Design; Circuit Design; Analog CAD; Analog HDL

We have developed an efficient design method for analog LSIs which performs simultaneous circuit and layout design with explicit consideration of performance constraints. The method is realized by three key technologies ; symbolic layout technique for layout recycling, performance driven automatic layout, and performance optimization technique according to stored design procedures.Our achievements are summarized as follows.1. Development of symbolic layout technique for layout recyclingWe have developed a symbolic layout technique that can update device shapes without design rule violation. The method can further optimize device shapes when they have multiple shape possibilities, so that overall layout space is minimized. This technique enables us to recycle previously designed layout for accommodating new performance specifications.2. Development of performance driven layout methods.In this project, we have devised a performance driven global routing method. The method treats all the nets simultaneously in every routing channel so that net ordering problem can be eliminated and globally optimized routing paths can be found. A concept of "routing possibility" and a resistor array model enable the simultaneous consideration.3. Development of a performance optimization technique which utilizes stored design procedures Design parameters are optimized according to design procedures which are acquired from a design process of a designer. A new design variable called an "uncertainty parameter" is introduced in order to describe a design procedure with less confidence. In case the optimization process fails, the system automatically modifies the uncertainty parameter so that the design process can continue.

我们已经开发出一种有效的设计方法，模拟LSI，同时进行电路和布局设计，明确考虑性能约束。该方法主要通过三个关键技术实现：面向版图回收的符号化版图技术、性能驱动的自动版图技术和基于存储设计过程的性能优化技术.开发了一种符号布局技术，可以在不违反设计规则的情况下更新器件形状。当器件形状具有多种形状可能性时，该方法可以进一步优化器件形状，使得总体布局空间最小化。这种技术使我们能够回收以前设计的布局，以适应新的性能规格。发展性能驱动的布图方法。在这个项目中，我们设计了一个性能驱动的全局布线方法。该方法同时处理每个布线通道中的所有网络，从而消除了网络排序问题，找到了全局最优的布线路径，并引入了“布线可能性”的概念和电阻阵列模型，实现了同时优化.开发利用存储的设计过程的性能优化技术根据从设计者的设计过程获取的设计过程来优化设计参数。引入了一个新的设计变量，称为“不确定性参数”，以描述一个设计过程的信心较低。在优化过程失败的情况下，系统自动修改不确定性参数，以便设计过程可以继续。

项目成果

H.Onodera: "Development of Module Generators from Extracted Design Procedures" IEICE Trans. Fundamentals. Vol.E78-A. 160-168 (1995)

H.Onodera：“从提取的设计程序开发模块生成器”IEICE Trans。

H. Onodera: "Compaction with Shape Optimization and its Application to Layout Recycling" IEICE Trans. Fundamentals. E78-A. 169-176 (1995)

H. Onodera：“形状优化压实及其在布局回收中的应用”IEICE Trans。

H.Onodera: "Global Routing Algorithm for Analog Circuits Using a Resistor Array Model" Proc.IEEE ISCAS. (to appear). (1996)

H.Onodera：“使用电阻阵列模型的模拟电路全局路由算法”Proc.IEEE ISCAS。

H. Onodera: "Grobal Routing Algorithm for Analog Circuits Using a Resistor Array Model" Proc. IEEE ISCAS発表予定. (1996)

H. Onodera：“使用电阻阵列模型的模拟电路的全局路由算法”Proc. IEEE ISCAS (1996)。

H.Onodera: "Compaction with Shape Optimization and its Application to Layout Recycling" IEICE Trans. Fundamentals. Vol.E78-A. 169-176 (1995)

H.Onodera：“形状优化压实及其在布局回收中的应用”IEICE Trans。