Research of a High-speed Signal Transmission Scheme for Integrated Circuits

本研究开发了一种设计方法，将GHz分发到芯片上的高速信号到每个LSI部分。研究课题仍在继续。一种技术来分析高速信号传输的电线的特性。一项技术来分析电力和地面线结构的特征学。一个用于高速信号传输的CMOS电路的设计方案。对芯片高速信号传输的未来性能预测。我们首先通过真正的芯片测量对其进行正交地面线评估。传统上，真正的地线在关于抵抗和诱导的讨论中被忽视。野外求解器的实际测量结果和结果显示原始接地线在高频率超过10千兆赫的情况下不可能。The Characteristic of transmission-lines depends on frequency。在电路模拟中的However，频率独立的互连模型是常见的。这就是为什么使用频率来连接模型的原因。 ... More 这是一个关键问题。我们开发了一种方法来确定基于单个频率的互连长度。当我们提取互连字符串时，我们将返回当前的分布对互连字符串有很大的影响。我们建议一种方法来选择电力/地面（p/g），它应该被认为是返回路径，我们讨论IR-drop aware p/g网格设计和开发一种方法来插入p/g straps。拟议的方法将以在低频率下操作电路的条件下，p/g电线的指数是不利的。由于频率的操作变得更高，p/g电线的作用对p/g噪声有显著的影响。我们用p/g网络的不同结构和不同操作条件来评估p/g噪声。实验结果显示在芯片上诱导成为p/g noise.Current mode logic（CML） realizes on-芯片高性能circuits。CML电路可以比传统静态CMOS逻辑电路更快地运行。我们还开发了一种由CML和静态CMOS组成的高速多路复用器的设计方法。设计的多路复用器是由真正的芯片测量验证的。相位锁定环路（PLL）也是高速电路中的重要组成部分。我们分析了通过改进制造过程的PLLs的性能趋势，我们大致评估了整个信号系统的性能，包括传输线、驱动程序电路和接收器电路。Less（低）

This research develops a design methodology to distribute GHz on chip high-speed signals to each portion of an LSI. The research topics are as follows.・A technique to analyze characteristics of wires for high-speed signal transmission.・A technique to analyze characteristics of power & ground-line structures.・A design scheme of CMOS circuits for a high-speed signal transmission.・Future performance predictions of on-chip high-speed signal transmission.We first evlauate on-chip transmission-lines with orthogonal ground wires by real chip measurement. Conventionally, orthogonal ground wires are ignored in the discussion about resistance and inductance. However measurement results and results of field solvers show orthogonal ground wires are not negligible in high frequency over 10GHz. The characteristic of transmission-lines depends on frequency. However in circuit simulation, frequency-independent interconnect model is commonly used. Therefore the frequency used to model interconnects is … More one of the crucial problems. We develop a method to decide the single frequency based on the interconnect length. When we extract the interconnect characteristics, return current distribution strongly affects to the interconnect characteristics. We propose a method to select power/ground(p/g) wires that should be considered as return-path.We discuss an IR-drop aware p/g grid design and develop a method to insert p/g straps. The proposed method targets the circuits operating at low frequency where the inductance of p/g wires are negligible. As the operating frequency becomes higher, the inductance of the p/g wires has significant effect to the p/g noise. We evaluate p/g noise with various structure of p/g net and various operating condition. Experimental results show when on-chip inductance become significant in p/g noise.Current mode logic(CML) realizes on-chip high performance circuits. CML circuits can operate faster than conventional static CMOS logic circuits. We also develop a design method for high-speed multiplexer composed of CML and static CMOS. Designed multiplexers are verified by real chip measurement. Phase-Locked-Loop(PLL) is also important component in high-speed circuits. We analyze the performance trend of PLLs by improvement of the fabrication process.Conclusively we evaluate the performance of whole signaling system includes transmission-line, driver circuit and receiver circuit. Less