Research of a High-speed Signal Transmission Scheme for Integrated Circuits

一种集成电路高速信号传输方案的研究

• 批准号: 14350186
• 负责人: ONODERA Hidetoshi
• 金额: $ 10.88万
• 依托单位: KYOTO UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 2002
• 资助国家: 日本
• 起止时间: 2002 至 2004
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-14350186/
• 关键词: Signal Transmission; LSI; SerDes; 配線特性; 高速信号伝達; オンチップ伝送線路; PLL; LC型PLL; リング型PLL; 性能予測; RLC抽出; LSI配線; 伝送線路; 配線構造; ドライバ駆動力; スパイラルインダクタ; 応答局面法

This research develops a design methodology to distribute GHz on chip high-speed signals to each portion of an LSI. The research topics are as follows.・A technique to analyze characteristics of wires for high-speed signal transmission.・A technique to analyze characteristics of power & ground-line structures.・A design scheme of CMOS circuits for a high-speed signal transmission.・Future performance predictions of on-chip high-speed signal transmission.We first evlauate on-chip transmission-lines with orthogonal ground wires by real chip measurement. Conventionally, orthogonal ground wires are ignored in the discussion about resistance and inductance. However measurement results and results of field solvers show orthogonal ground wires are not negligible in high frequency over 10GHz. The characteristic of transmission-lines depends on frequency. However in circuit simulation, frequency-independent interconnect model is commonly used. Therefore the frequency used to model interconnects is … More one of the crucial problems. We develop a method to decide the single frequency based on the interconnect length. When we extract the interconnect characteristics, return current distribution strongly affects to the interconnect characteristics. We propose a method to select power/ground(p/g) wires that should be considered as return-path.We discuss an IR-drop aware p/g grid design and develop a method to insert p/g straps. The proposed method targets the circuits operating at low frequency where the inductance of p/g wires are negligible. As the operating frequency becomes higher, the inductance of the p/g wires has significant effect to the p/g noise. We evaluate p/g noise with various structure of p/g net and various operating condition. Experimental results show when on-chip inductance become significant in p/g noise.Current mode logic(CML) realizes on-chip high performance circuits. CML circuits can operate faster than conventional static CMOS logic circuits. We also develop a design method for high-speed multiplexer composed of CML and static CMOS. Designed multiplexers are verified by real chip measurement. Phase-Locked-Loop(PLL) is also important component in high-speed circuits. We analyze the performance trend of PLLs by improvement of the fabrication process.Conclusively we evaluate the performance of whole signaling system includes transmission-line, driver circuit and receiver circuit. Less

本研究开发一种设计方法，以分配GHz的片上高速信号的LSI的每个部分。研究课题如下：·一种分析高速信号传输导线特性的技术。·一种分析电源和地线结构特性的技术。·一种用于高速信号传输的CMOS电路设计方案。片上高速信号传输的未来性能预测。我们首先通过真实的芯片测量来评估具有正交地线的片上传输线。传统上，在讨论电阻和电感时忽略了正交地线。然而，测量结果和场解算器的结果表明，正交接地线在10 GHz以上的高频中是不可忽略的。传输线的特性取决于频率。然而，在电路仿真中，频率无关的互连线模型是常用的。因此，用于对互连建模的频率为 ...更多信息 关键问题之一。提出了一种根据互连线长度确定单频的方法。在提取互连线特征时，返回电流分布对互连线特征有很大的影响。提出了一种选择电源/地线作为返回路径的方法，讨论了一种具有IR压降的p/g栅设计，并提出了一种插入p/g带的方法。所提出的方法针对的电路工作在低频的p/g线的电感可以忽略不计。随着工作频率的提高，p/g线的电感对p/g噪声有显著的影响。我们评估了不同结构的p/g网和不同工作条件下的p/g噪声。实验结果表明，当片上电感对p/g噪声影响较大时，电流模式逻辑（CML）实现了片上高性能电路。CML电路可以比传统的静态CMOS逻辑电路更快地操作。提出了一种由CML和静态CMOS构成的高速多路复用器的设计方法。设计的多路复用器通过真实的芯片测量进行了验证。锁相环（PLL）也是高速电路中的重要组成部分。分析了锁相环在工艺改进后的性能变化趋势，最后对整个信号系统包括传输线、驱动电路和接收电路的性能进行了评估。少

项目成果

土谷, 橋本, 小野寺: "VLSI配線の伝送線路特性を考慮した駆動力決定手法"情報処理学会論文誌. 43・5. 1338-1347 (2002)

土屋、桥本、小野寺：“考虑VLSI布线的传输线特性的驱动力确定方法”日本信息处理学会会刊43・5（2002）。

H.Hoshino, K.Okada, H.Onodera: "Design Optimization Methodology of On-Chip Spiral Inductor"Proc.SASIMI. (発表予定).

H.Hoshino、K.Okada、H.Onodera：“片上螺旋电感器的设计优化方法”Proc.SASIMI（待提交）。

On-Chip Global Signaling by Wave Pipelining

通过 Wave Pipelines 进行片上全局信令

• 发表时间: 2004
• 期刊: Proc.of IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging
• 作者: M.Hashimoto;A.Tsuchiya;H.Onodera
• 通讯作者: H.Onodera

A.Tsuchiya, M.Hashimoto, H.Onodera: "Representative Frequency for Interconnect R(f)L(f)C Extraction"IEICE Transactions on Fundamentals. E86-A,12. 2942-2951 (2003)

A.Tsuchiya、M.Hashimoto、H.Onodera：“互连 R(f)L(f)C 提取的代表性频率”IEICE 基本交易。

A.Tsuchiya, M.Hashimoto, H.Onodera: "Representative Frequency for Interconnect R(f)L(f)C Extraction"Proc. Asia and South Pacific Design Automation Conference. 691-696 (2004)

A.Tsuchiya、M.Hashimoto、H.Onodera：“互连 R(f)L(f)C 提取的代表频率”Proc。