Research of a High-speed Signal Transmission Scheme for Integrated Circuits

一种集成电路高速信号传输方案的研究

• 批准号: 14350186
• 负责人: ONODERA Hidetoshi
• 金额: $ 10.88万
• 依托单位: KYOTO UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 2002
• 资助国家: 日本
• 起止时间: 2002 至 2004
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-14350186/
• 关键词: Signal Transmission; LSI; SerDes; 配線特性; 高速信号伝達; オンチップ伝送線路; PLL; LC型PLL; リング型PLL; 性能予測; RLC抽出; LSI配線; 伝送線路; 配線構造; ドライバ駆動力; スパイラルインダクタ; 応答局面法

This research develops a design methodology to distribute GHz on chip high-speed signals to each portion of an LSI. The research topics are as follows.・A technique to analyze characteristics of wires for high-speed signal transmission.・A technique to analyze characteristics of power & ground-line structures.・A design scheme of CMOS circuits for a high-speed signal transmission.・Future performance predictions of on-chip high-speed signal transmission.We first evlauate on-chip transmission-lines with orthogonal ground wires by real chip measurement. Conventionally, orthogonal ground wires are ignored in the discussion about resistance and inductance. However measurement results and results of field solvers show orthogonal ground wires are not negligible in high frequency over 10GHz. The characteristic of transmission-lines depends on frequency. However in circuit simulation, frequency-independent interconnect model is commonly used. Therefore the frequency used to model interconnects is … More one of the crucial problems. We develop a method to decide the single frequency based on the interconnect length. When we extract the interconnect characteristics, return current distribution strongly affects to the interconnect characteristics. We propose a method to select power/ground(p/g) wires that should be considered as return-path.We discuss an IR-drop aware p/g grid design and develop a method to insert p/g straps. The proposed method targets the circuits operating at low frequency where the inductance of p/g wires are negligible. As the operating frequency becomes higher, the inductance of the p/g wires has significant effect to the p/g noise. We evaluate p/g noise with various structure of p/g net and various operating condition. Experimental results show when on-chip inductance become significant in p/g noise.Current mode logic(CML) realizes on-chip high performance circuits. CML circuits can operate faster than conventional static CMOS logic circuits. We also develop a design method for high-speed multiplexer composed of CML and static CMOS. Designed multiplexers are verified by real chip measurement. Phase-Locked-Loop(PLL) is also important component in high-speed circuits. We analyze the performance trend of PLLs by improvement of the fabrication process.Conclusively we evaluate the performance of whole signaling system includes transmission-line, driver circuit and receiver circuit. Less

本研究开发了一种设计方法，将GHz片上高速信号分配到LSI的每个部分。研究课题如下：一种分析用于高速信号传输的导线特性的技术。一种分析电力和地线结构特性的技术。一种用于高速信号传输的CMOS电路设计方案。·片上高速信号传输的未来性能预测。我们首先通过实际的芯片测量来评估具有正交地线的片上传输线。在讨论电阻和电感时，通常忽略正交地线。然而，测量结果和现场求解结果表明，在10GHz以上的高频中，正交地线是不可忽略的。传输线的特性取决于频率。但在电路仿真中，常用的是与频率无关的互连模型。因此，用于对互连进行建模的频率是至关重要的问题之一。我们提出了一种基于互连长度来确定单频的方法。在提取互连特性时，回流电流分布对互连特性有很大影响。我们提出了一种选择电源/地（p/g）线作为回程路径的方法。我们讨论了一种可感知红外跌落的p/g栅格设计，并开发了一种插入p/g带的方法。该方法适用于p/g导线电感可以忽略不计的低频电路。随着工作频率的提高，p/g线的电感对p/g噪声有显著的影响。我们用不同的p/g网结构和不同的运行条件来评价p/g噪声。实验结果表明，片上电感在p/g噪声下变得显著。电流模式逻辑（CML）实现了片上高性能电路。CML电路比传统的静态CMOS逻辑电路运行速度更快。本文还提出了一种由CML和静态CMOS组成的高速多路复用器的设计方法。设计的多路复用器通过实际芯片测量得到了验证。锁相环（PLL）也是高速电路中的重要组成部分。通过改进制造工艺，分析了锁相环的性能趋势。最后对整个信号系统的性能进行了评估，包括传输在线、驱动电路和接收电路。少

项目成果

土谷, 橋本, 小野寺: "VLSI配線の伝送線路特性を考慮した駆動力決定手法"情報処理学会論文誌. 43・5. 1338-1347 (2002)

土屋、桥本、小野寺：“考虑VLSI布线的传输线特性的驱动力确定方法”日本信息处理学会会刊43・5（2002）。

H.Hoshino, K.Okada, H.Onodera: "Design Optimization Methodology of On-Chip Spiral Inductor"Proc.SASIMI. (発表予定).

H.Hoshino、K.Okada、H.Onodera：“片上螺旋电感器的设计优化方法”Proc.SASIMI（待提交）。

On-Chip Global Signaling by Wave Pipelining

通过 Wave Pipelines 进行片上全局信令

• 发表时间: 2004
• 期刊: Proc.of IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging
• 作者: M.Hashimoto;A.Tsuchiya;H.Onodera
• 通讯作者: H.Onodera

A.Tsuchiya, M.Hashimoto, H.Onodera: "Representative Frequency for Interconnect R(f)L(f)C Extraction"IEICE Transactions on Fundamentals. E86-A,12. 2942-2951 (2003)

A.Tsuchiya、M.Hashimoto、H.Onodera：“互连 R(f)L(f)C 提取的代表性频率”IEICE 基本交易。

A.Tsuchiya, M.Hashimoto, H.Onodera: "Representative Frequency for Interconnect R(f)L(f)C Extraction"Proc. Asia and South Pacific Design Automation Conference. 691-696 (2004)

A.Tsuchiya、M.Hashimoto、H.Onodera：“互连 R(f)L(f)C 提取的代表频率”Proc。