Development of Statistical Performance Analysis and Optimization Methods for Large Scale Integrated Circuits

随着大规模集成电路制造技术的不断进步，由于制造条件的波动而引起的器件特性的可变性对电路性能产生了很大的影响。器件特性的可变性不能通过调整制造工艺来完全消除，因此需要一种从根本上考虑可变性的新的设计优化方法。在本研究中，我们开发了四种方法作为基础和应用技术来统计分析和优化电路性能；1)器件特性变异性的建模技术，2)大型模拟电路的统计性能分析方法和电路优化技术，3)数字电路的最坏情况分析方法，4)统计静态时序分析方法和性能优化技术。1)提出了一种从物理参数的可变性到设备参数的可变性的转换方法。我们设计了两个模型来表示变量；一种是晶圆上的系统变量，另一种是局部随机变量。我们还为这两种类型的变量开发了一种测量方法。2)对于大型模拟电路的统计性能分析，我们开发了一种将器件特性可变性与系统级性能可变性联系起来的方法。该方法为每个层次构建响应面，并链接派生的响应面。利用1)的建模技术，我们可以得到物理参数的可变性与系统级性能可变性之间的关系。我们还开发了一种分层自顶向下设计风格的良率优化方法。3)建立了一种延迟计算模型，称为矢量合成模型。该模型能以较小的计算量计算出实际最坏情况下的延迟时间。我们还设计了一种方法，可以通过查找预表征参考表，立即导出大型电路的矢量综合模型。4)提出了统计静态时序分析方法。该方法将时延计算中的不确定性作为统计变量，推导出电路中每个节点的概率分布。然后我们得到了电路延迟的概率分布。我们还开发了一种最小化最坏情况延迟的性能优化方法。少

With steady improvement in LSI fabrication technology, variabilities of device characteristics, which are caused by fluctuation of manufacturing conditions, affect circuit performance considerably. The variabilities of device characteristics can not be completely eliminated by tuning fabrication processes, and hence a new design optimization methodology that can fundamentally consider the variabilities is necessary.In this research, we develop four methods as fundamental and application techniques to analyze and optimize circuit performance statistically; 1) a modeling technique of the variabilities of device characteristics, 2) a statistical performance analysis method and a circuit optimization technique for large analog circuits, 3) a worst-case analysis method for digital circuits, 4) a statistical static timing analysis method and a performance optimization technique.1) We develop a transformation method from the variabilities of physical parameters to the variabilities of device … More characteristics using an intermediate model. We devise two models that represent the variabilities; one is for systematic variabilities on a wafer, and the other is for local random variabilities. We also develop a measurement method for both types of the variabilities.2) As for statistical performance analysis for large analog circuits, we develop a method that links the device characteristics variabilities to the system-level performance variabilities. This method builds a response surface for each hierarchy, and links the derived response surfaces. With the modeling techniques of 1), we can obtain the relationship between the variabilities of physical parameters and the system-level performance variabilities. We also develop an yield optimization method for hierarchical top-down design style.3) We develop a delay calculation model called vector synthesis model. This model can calculate practical worst-case delay time with small computational costs. We also devise a method that instantly derives vector synthesis models of large circuits looking up pre-characterized reference tables.4) We develop a statistical static timing analysis method. This method treats the uncertainties in delay calculation as statistical variables, and the derives a probability distribution at every node in a circuit. We then obtain the probability distribution of the circuit delay. We also develop a performance optimization method that minimizes the worst-case delay. Less