Development of Statistical Performance Analysis and Optimization Methods for Large Scale Integrated Circuits

大规模集成电路统计性能分析和优化方法的发展

• 批准号: 11555095
• 负责人: ONODERA Hidetoshi
• 金额: $ 7.42万
• 依托单位: KYOTO UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1999
• 资助国家: 日本
• 起止时间: 1999 至 2001
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-11555095/
• 关键词: Manufacturing Variability; Statistical Analysis; Statistical Timing Analysis; Intra-Chip Variability; Inter-Chip Variability; VLSI; Hierarchical Design; Analog Circuit; 統計的解析; ばらつき; 集積回路; 歩留り最大化; ロバスト設計; 設計容易化技術; 統計モデリング; モンテカルロ解析

With steady improvement in LSI fabrication technology, variabilities of device characteristics, which are caused by fluctuation of manufacturing conditions, affect circuit performance considerably. The variabilities of device characteristics can not be completely eliminated by tuning fabrication processes, and hence a new design optimization methodology that can fundamentally consider the variabilities is necessary.In this research, we develop four methods as fundamental and application techniques to analyze and optimize circuit performance statistically; 1) a modeling technique of the variabilities of device characteristics, 2) a statistical performance analysis method and a circuit optimization technique for large analog circuits, 3) a worst-case analysis method for digital circuits, 4) a statistical static timing analysis method and a performance optimization technique.1) We develop a transformation method from the variabilities of physical parameters to the variabilities of device … More characteristics using an intermediate model. We devise two models that represent the variabilities; one is for systematic variabilities on a wafer, and the other is for local random variabilities. We also develop a measurement method for both types of the variabilities.2) As for statistical performance analysis for large analog circuits, we develop a method that links the device characteristics variabilities to the system-level performance variabilities. This method builds a response surface for each hierarchy, and links the derived response surfaces. With the modeling techniques of 1), we can obtain the relationship between the variabilities of physical parameters and the system-level performance variabilities. We also develop an yield optimization method for hierarchical top-down design style.3) We develop a delay calculation model called vector synthesis model. This model can calculate practical worst-case delay time with small computational costs. We also devise a method that instantly derives vector synthesis models of large circuits looking up pre-characterized reference tables.4) We develop a statistical static timing analysis method. This method treats the uncertainties in delay calculation as statistical variables, and the derives a probability distribution at every node in a circuit. We then obtain the probability distribution of the circuit delay. We also develop a performance optimization method that minimizes the worst-case delay. Less

随着大规模集成电路制造技术的不断进步，由于制造条件的波动而引起的器件特性的变化对电路性能有很大的影响。器件特性的不稳定性不能通过调整工艺完全消除，因此需要一种新的能从根本上考虑不稳定性的设计优化方法，在本研究中，我们发展了四种方法作为统计分析和优化电路性能的基础和应用技术; 1）器件特性变化的建模技术，2）大型模拟电路的统计性能分析方法和电路优化技术，3）数字电路的最坏情况分析方法; 4）统计静态时序分析方法和性能优化技术; 1）提出了一种从物理参数的不确定性到器件的不确定性的转换方法 ...更多信息 使用中间模型的特性。我们设计了两个模型，代表的变异性，一个是系统的变异性的晶片上，另一个是局部随机变异性。2）对于大型模拟电路的统计性能分析，提出了一种将器件特性变量与系统级性能变量联系起来的方法。该方法为每个层次结构构建响应面，并链接派生的响应面。利用1）的建模技术，我们可以得到物理参数的变化与系统级性能变化之间的关系。3）提出了一种延迟计算模型--向量综合模型。该模型可以计算实际的最坏情况下的延迟时间与小的计算成本。我们还设计了一种方法，立即获得向量综合模型的大型电路查找预先特征化的参考表。4）我们开发了一种统计静态时序分析方法。该方法将时延计算中的不确定性作为统计量，导出电路中每个节点的概率分布。然后，我们得到的电路延迟的概率分布。我们还开发了一种性能优化方法，最大限度地减少最坏情况下的延迟。少

项目成果

Takeo Yasuda: "A Dynamically Phase Adjusting PLL with a Variable Delay"Proc. Asia and South Pacific Design Automation Conference. 275-280 (2001)

Takeo Yasuda：“具有可变延迟的动态相位调整 PLL”Proc。

Kenichi Okada: "Statistical Modeling of Device Characteristics with Systematic Fluctuation"Proc. IEEE International Symposium on Circuits and systems. Vol.II. 437-440 (2000)

Kenichi Okada：“具有系统波动的器件特性的统计建模”Proc。

T.Fujita,H.Onodera et.al.: "A Method for Linking Process-level Variability to System Performances"Proc of the Asia and South Pacific Design Automation Conference 2000. 547-551 (2000)

T.Fujita, H.Onodera 等人：“A Method for Linking Process-level Variability to System Performances”Proc of the Asia and South Pacific Design Automation Conference 2000. 547-551 (2000)

K.Okada,H.Onodera: "Stastical Modeling of Device Characteristics with Systematic Variability"IEICE Transacions on Fundamentals. E84-A(2). 529-536 (2001)

K.Okada、H.Onodera：“具有系统变异性的设备特性的统计建模”IEICE Transacions 基础知识。

藤田智弘,小野寺秀俊: "大規模集積回路の統計的遅延解析手法"情報処理学会DAシンポジウム2000論文集. 91-96 (2000)

Tomohiro Fujita、Hidetoshi Onodera：“大规模集成电路的统计延迟分析方法”日本信息处理协会 DA 研讨会 2000 年论文集 91-96 (2000)。