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Fundamental Study on Low-loss SiC Power Devices Using Multi pn Junctions

使用多pn结的低损耗SiC功率器件的基础研究

基本信息

批准号：
16360153
负责人：
KIMOTO Tsunenobu
金额：
$ 9.66万
依托单位：
KYOTO UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2004
资助国家：
日本
起止时间：
2004 至 2005
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-16360153/
关键词：
Silicon Carbide Power Device MOSFET Multi pn Junction RESURF Structure デバイスシミュレーション

项目摘要

In this research project, designing and fabrication of low-loss, high-voltage silicon carbide (SiC) power devices with multi pn junction structures have been investigated. In the multi pn junction structures, two- or three-dimensional extension of space charge regions enables the usage of highly doped semiconductors, by which on-state resistance can be significantly reduced. This is the first investigation on SiC power devices with such structures. As a typical device, lateral high-voltage MOSFETs have been investigated.Effects of doping concentration of each region on breakdown voltage and on-resistance of SiC RESURF (Reduced Surface Field) MOSFETs have been analyzed by using a two-dimensional device simulator. Effective charge at the MOS interface influences the space charge region and thereby breakdown voltage. Optimum dose designing and its guideline have been determined. Double RESURF structure with a pnp layer structure is effective to reduce on-resistance. The breakdown voltage can be increased because the electric field inside the oxide is reduced.SiC Lateral RESURF MOSFETs have been fabricated on 10 μm-thick p-type epilayers. Ion implantation was employed to form RESURF, top-p, source, and drain regions. The gate oxide was grown by direct oxidation in N_3O at 1300℃. The typical channel length, RESURF length were 2〜3μm and 20μm, respectively. An original self-aigned process has been developed to fabricate double RESURF MOSFETs. A single-zone double RESURF MOSFET fabricated in this study exhibited a breakdown voltage of 750 V and a low on-resistance of 52 mΩcm^2. The original two-zone double RESURF MOSFET showed characteristics of 1380 V - 66mΩcm^2, which is the pest performance among any lateral MOSFETs ever reported.

本研究计画主要针对具有多pn结结构的低损耗、高电压碳化硅功率元件进行设计与制作。在多pn结结构中，空间电荷区的二维或三维延伸使得能够使用高掺杂半导体，由此可以显著降低导通电阻。这是首次对这种结构的SiC功率器件进行研究。本文以横向高压MOSFET为研究对象，利用二维器件模拟器分析了SiC RESURF（Reduced Surface Field）MOSFET各区域掺杂浓度对器件击穿电压和导通电阻的影响。MOS界面处的有效电荷影响空间电荷区，从而影响击穿电压。确定了最佳剂量设计方案及其指导原则。具有pnp层结构的双RESURF结构对于减小导通电阻是有效的。在10 μ m厚的p型外延层上制备了SiC横向RESURF MOSFET。采用离子注入形成RESURF、顶部p、源极和漏极区。栅氧化层是在1300℃的N_3O气氛中直接氧化生长的。典型沟道长度为2 ~ 3μm，RESURF长度为20μm。提出了一种新颖的自对准工艺来制作双RESURF MOSFET。本研究中制作的单区双RESURF MOSFET的击穿电压为750 V，导通电阻为52 mΩ cm ^2。原始的双区双RESURF MOSFET显示出1380 V -66 m Ω cm ^2的特性，这是迄今为止报道的所有横向MOSFET中最差的性能。

项目成果

期刊论文数量（26）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

1330V,67mΩcm^2 4H-SiC(0001)RESURF MOSFET

1330V，67mΩcm^2 4H-SiC(0001)RESURF MOSFET

DOI：
发表时间：
2005
期刊：
IEEE Electron Device Lett. Vol.26
影响因子：
0
作者：
H. Matsui;H. Tabata;H.Matsui;T.Kimoto他;H.Matsui;S. T. Mahmuda;T.Kimoto他;T.Kimoto他;H. Matsui;T.Kimoto
通讯作者：
T.Kimoto

Characterization of in-grown stacking faults in 4H-SiC(0001) epitaxial layers and its impacts on high-voltage Schottky diodes

4H-SiC(0001)外延层内生堆垛层错的表征及其对高压肖特基二极管的影响

DOI：
发表时间：
2005
期刊：
Appl.Phys.Lett. Vol.87
影响因子：
0
作者：
H. Matsui;H. Tabata;H.Matsui;T.Kimoto他;H.Matsui;S. T. Mahmuda;T.Kimoto他;T.Kimoto他;H. Matsui;T.Kimoto;T. Ohtake;H. Matsui;T.Kimoto;K. Kotani;T.Kimoto;T. Kawahara;T.Kimoto;H. Matsui;T.Kimoto;松井裕章;T.Kimoto
通讯作者：
T.Kimoto

Interface properties of metal-oxide-semiconductor structureson 4H-SiC{0001} and (1120) formed by N_2O oxidation

N_2O氧化形成的4H-SiC{0001}和(1120)金属-氧化物-半导体结构的界面特性

DOI：
发表时间：
2005
期刊：
Jpn.J.Appl.Phys. 44
影响因子：
0
作者：
Junli Wang;Liwei Zhao;Nam Hoai Luu;Dong Wang;Hiroshi Nakashima;H. Matsui;H. Matsui;Kimoto他;T.Kimoto他
通讯作者：
T.Kimoto他

Design and fabrication of RESURF MOSFETs on 4H-SiC(0001), (112~0), and 6H-SiC(0001)