LSI Test Technology for Evaluating Soft-Error-Rates in Combinational Logic Circuits

当暴露在辐射环境中时，超大规模集成电路（vlsi）会出现称为“软误差”的瞬态误差。由于晶体管的积极小型化，软误差现在正成为像cpu这样的逻辑vlsi的严重故障来源。因此，需要对辐照试验中制备的逻辑芯片的实验软误差率进行评估。为此，我们在本研究项目中开发了一种新的大规模集成电路测试技术。为了准确地评估逻辑芯片的软错误率，必须满足以下两个要求。逻辑vlsi由复杂的组合逻辑电路网络组成，由逆变器等逻辑门和触发器等顺序元件组成。它需要计算出分散在芯片中的每个顺序元件上存储数据的辐射引起的扰动的数量。此外，数据扰动不仅是由对序列元件的直接辐射撞击引起的，而且还由对组合逻辑电路的辐射撞击产生的被称为“单事件瞬态，set”的锁存脉冲型噪声引起的。前者通常被称为“顺序元件中的软错误”，后者被称为“组合逻辑电路中的软错误”。评估软误差对组合逻辑电路的影响尤为重要。这两种类型的软错误应该分别评估。我们的测试技术基于扫描测试技术，扫描测试技术在当今的逻辑芯片中广泛用于测试其操作，因为它使我们能够直接写入和读取每个顺序元素。我们开发了一种扫描触发器电路和一种辐射测试方法来评估软错误率。我们已经用实验证明了这项技术的有效性。此外，我们还成功地揭示了SOI-CMOS逻辑门中SET的详细脉宽分布，并开发了一种快速准确的SET波形估计技术。

Very large scale integrations, VLSIs, exhibit transient errors called "soft errors" when exposed to radiation environments. As a result of aggressive miniaturization of transistors, the soft error is now becoming a serious failure source of logic VLSIs like CPUs. It is thus desired to evaluate experimentally soft-error rates of fabricated logic chips in irradiation tests. For the purpose, we have developed a new LSI test technology in this research project.To evaluate soft-error rates of logic chips precisely, the following two requirements should he satisfied. Logic VLSIs consist of complicated networks of combinational logic circuits built with logic gates like inverters and sequential elements like flip-flops. It is required to count up the number of radiation-induced upsets of stored data at each sequential element scattered in the chips. Moreover, the data upsets are induced by not only direct radiation hits to the sequential elements and also latching pulse-type noises named "single-event transients, SETs, " which are generated by radiation hits to combinational logic circuits. The former is generally called "soft errors in sequential elements, " and the latter "soft errors in combinational logic circuits." It is now important to evaluate the impact of the soft errors in combinational logic circuits in particular. These both types of soft errors should be evaluated separately.Our test technology is based on the scan test technology, which is widely used in today's logic chips for testing their operations because it enables us to write and read each sequential element directly. We have developed a scan flip- flop circuit and an irradiation test method for the soft-error rates evaluation. We have experimentally demonstrated the validity of the technology. Moreover, we have successfully revealed detailed pulse-width distributions of SETs in SOI-CMOS logic gates, and developed a fast and accurate estimation technique of SET waveforms.