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LSI Test Technology for Evaluating Soft-Error-Rates in Combinational Logic Circuits

LSI Test Technology for Evaluating Soft-Error-Rates in Combinational Logic Circuits
用于评估组合逻辑电路中软错误率的 LSI 测试技术
批准号:
18560359
负责人:
KOBAYASHI Daisuke
金额:
$2.34万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
2006
资助国家:
日本
项目状态:
已结题
起止时间:
2006 至 2007

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中文摘要
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英文摘要
Very large scale integrations, VLSIs, exhibit transient errors called "soft errors" when exposed to radiation environments. As a result of aggressive miniaturization of transistors, the soft error is now becoming a serious failure source of logic VLSIs like CPUs. It is thus desired to evaluate experimentally soft-error rates of fabricated logic chips in irradiation tests. For the purpose, we have developed a new LSI test technology in this research project.To evaluate soft-error rates of logic chips precisely, the following two requirements should he satisfied. Logic VLSIs consist of complicated networks of combinational logic circuits built with logic gates like inverters and sequential elements like flip-flops. It is required to count up the number of radiation-induced upsets of stored data at each sequential element scattered in the chips. Moreover, the data upsets are induced by not only direct radiation hits to the sequential elements and also latching pulse-type noises named "single-event transients, SETs, " which are generated by radiation hits to combinational logic circuits. The former is generally called "soft errors in sequential elements, " and the latter "soft errors in combinational logic circuits." It is now important to evaluate the impact of the soft errors in combinational logic circuits in particular. These both types of soft errors should be evaluated separately.Our test technology is based on the scan test technology, which is widely used in today's logic chips for testing their operations because it enables us to write and read each sequential element directly. We have developed a scan flip- flop circuit and an irradiation test method for the soft-error rates evaluation. We have experimentally demonstrated the validity of the technology. Moreover, we have successfully revealed detailed pulse-width distributions of SETs in SOI-CMOS logic gates, and developed a fast and accurate estimation technique of SET waveforms.
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Time-domain component analysis of heavy-ion-induced transient currents in fully-depleted SOI MOSFETs
全耗尽 SOI MOSFET 中重离子感应瞬态电流的时域分量分析
DOI: --
发表时间: 2006
期刊: IEEE Transactions on Nuclear Science 53
影响因子: --
作者: [D.Kobayashi, et. al.]
通讯作者: et. al.
Estimation of single event transient voltage pulses in VLST circuits from heavy-ion-induced transients measured in a single MOSFET
根据在单个 MOSFET 中测量的重离子感应瞬态来估计 VLST 电路中的单事件瞬态电压脉冲
DOI: --
发表时间: 2007
期刊: IEEF Transactions on Nuclear Science 54(4)(印刷中)
影响因子: --
作者: [松本 光崇, 木村 峻, 中野 裕文, 岩男 剛宜, 奥野 義弘, 有本 和民, 泉 知論, 藤野 毅, 知念 幸勇, 出川直通, D.Kobayashi et al.]
通讯作者: D.Kobayashi et al.
宇宙用SOI半導体部品の処理能力向上のための放射線誘起過渡現象の研究
研究辐射引起的瞬态现象以提高太空用 SOI 半导体元件的产量
DOI: --
发表时间: 2006
期刊:
影响因子: --
作者: [小林大輔, 他]
通讯作者:
0.2μm FD-SOI論理セルにおけるシグナルイベント・トランジェントのパル幅測定
0.2μm FD-SOI 逻辑单元中信号事件和瞬态的脉冲宽度测量
DOI: --
发表时间: 2006
期刊: 第7回半導体の放射線照射効果研究会
影响因子: --
作者: [松本 光崇, 石橋 宏太, 木村 峻, 大山 昇吾, 泉 知論, 藤野 毅, 岩男 剛宜, 中野 裕文, 奥野 義弘, 有本 和民, 宇田川夏海, 柳川善光 他]
通讯作者: 柳川善光 他
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