Designing of Ultra High-Speed and Compact Variable Latency PipelinedArithmetic Units

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To realize low-power and high-speed arithmetic units with future CMOS technologies, this project focused on and carried out research that concerned with a circuit compaction technique and a delay balancing technique. An input bit-sliced circuit partitioning method for circuit scale compaction and a delay balancing methods based on logical effort theory for wave pipelines have been proposed and evaluated. The experimental results clarified the effective of both proposals.