Designing of Ultra High-Speed and Compact Variable Latency PipelinedArithmetic Units

为了利用未来的CMOS技术实现低功耗、高速度的运算器，本课题重点研究了电路紧凑技术和时延均衡技术。提出了一种用于电路规模压缩的输入比特切片电路划分方法和一种基于逻辑功率论的波状流水线延迟平衡方法，并对其进行了评价。实验结果验证了这两种方法的有效性。

To realize low-power and high-speed arithmetic units with future CMOS technologies, this project focused on and carried out research that concerned with a circuit compaction technique and a delay balancing technique. An input bit-sliced circuit partitioning method for circuit scale compaction and a delay balancing methods based on logical effort theory for wave pipelines have been proposed and evaluated. The experimental results clarified the effective of both proposals.