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Multi-layer I/O chip architecture enabled by back end of line compatible switch for increased data handling density

Multi-layer I/O chip architecture enabled by back end of line compatible switch for increased data handling density
多层 I/O 芯片架构由后端兼容交换机实现,可提高数据处理密度
批准号:
561133-2020
负责人:
Barlage, Douglas
金额:
$3.64万
依托单位:
依托单位国家:
加拿大
项目类别:
Alliance Grants
财政年份:
2020
资助国家:
加拿大
项目状态:
已结题
起止时间:
2020-01-01 至 2021-12-31

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英文摘要
Alberta and Canada have a strong and time-sensitive opportunity to be leaders in the effort to vastly improve data handling densities at the electronic level and significantly impact the global Internet of Things (IoT) industry. The goal of this project is to unlock new capabilities of IoT electronics by massively increasing data handling capabilities in key parts of the IoT infrastructure at the electronic level. This will be achieved by incorporating a novel Alberta developed metal oxide thin-film transistor (MOTFT) switch device that allows for multiple layers of data input/output (IO) channels to be stacked in a 3D monolithically integrated multi-tiered IO chip architecture (3DMIO). The result is a compact 3DMIO chip with, in this iteration, double the data IO density within the same surface area of a single chip. This density enhancement is seen as a key enabler in the $450 Billion dollar semiconductor industry in beyond Moore's law devices. The switch effectively works as a glue between disparate technologies that are part of the IoT infrastructure such as traditional advanced logic, sensor networks, memory, communications, neuromorphic and potentially quantum computing. The functional advantage of the MOTFT switch enabling a 3D monolithic architecture for IoT is the realization of heterogeneous technologies operating with different link power bus and data communication link requirements all within a single chip. The functional advantage of the MOTFT switch will be demonstrated through its integration within the final 3DMIO chip prototype that will be built by the end of the project.
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Multi-layer I/O chip architecture enabled by back end of line compatible switch for increased data handling density
  • 批准号:
    561133-2020
  • 项目类别:
    Alliance Grants
  • 资助金额:
    $3.64万
  • 财政年份:
    2021
  • 负责人:
    Barlage, Douglas
  • 依托单位:
Wide Band Gap Semiconductors for Flexible Power Applications
  • 批准号:
    RGPIN-2015-04709
  • 项目类别:
    Discovery Grants Program - Individual
  • 资助金额:
    $1.82万
  • 财政年份:
    2019
  • 负责人:
    Barlage, Douglas
  • 依托单位:
Wide Band Gap Semiconductors for Flexible Power Applications
  • 批准号:
    RGPIN-2015-04709
  • 项目类别:
    Discovery Grants Program - Individual
  • 资助金额:
    $1.82万
  • 财政年份:
    2018
  • 负责人:
    Barlage, Douglas
  • 依托单位:
Wide Band Gap Semiconductors for Flexible Power Applications
  • 批准号:
    RGPIN-2015-04709
  • 项目类别:
    Discovery Grants Program - Individual
  • 资助金额:
    $1.82万
  • 财政年份:
    2017
  • 负责人:
    Barlage, Douglas
  • 依托单位:
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