NSF Workshop on Challenges and Opportunities in Gig-Scale Integration for System-On-A-Chip

这次研讨会由国家科学基金会和台湾国家科学委员会主办，旨在评估千兆级(纳米)技术设计和验证方面的挑战和关键研究需求。技术的快速扩展实现了非常高的芯片集成度。不久，将复杂的电子系统集成到一块芯片上将是可行的，包括微处理器、嵌入式存储器、可编程逻辑和各种专用电路元件。然而，目前还没有经过验证的设计方法和工具来支持这种千兆规模的设计和集成。正在解决的研究问题是：如何在纳米设计中提供充分的设计抽象，考虑到电气细节？如何表示和表征可以跨越技术、代工和设计环境的边界使用的可复用块？如何对不同功能块的交互作用进行建模以进行整体模拟和优化？如何在功能规范和性能约束下证明“已知良好的设计”？研讨会报告载有研讨会关于有希望的创新机会的调查结果的说明，以及关于将要进行的研究的风格和种类的建议。委员会就如何落实这些建议，向社会人士提出意见和建议。

This workshop, sponsored by the National Science Foundation and the National Science Council of Taiwan, is an assessment of the challenges and critical research needs of design and verification in giga-scale (nanometer) technologies. Rapid scaling of technologies enables a very high degree of chip integration. It will soon be feasible to integrate a complex electronic system on onto a chip, including microprocessors, embeddedmemories, programmable logics, and various application specific circuit components. However, there is no proven design methodology and tools to support such giga-scale design and integration. Research questions being addressed are: How to provide sufficient design abstraction which takes into consideration the electrical details in nanometer design?; How to represent and characterize reusable blocks which can be used across the boundaries of technology generations, foundries and design environments?; How to model the interaction of heterogeneous functional blocks for overall simulation and optimization?; How to certify "known good design" under functional specification and performance constraints? The workshop report contains a statement of the workshop findings with regard to promising opportunities for innovation, and recommendations regarding the style and kind of research to be conducted. It identifies and suggestions to the community as to how to implement the recommendations.