POWRE: Nano-gate Engineering for Ultra-fast CMOS devices

为了从纳米级的cmos器件中获得最大的性能，传统的多晶硅栅极将不得不被金属层所取代。然而，任何替代多晶硅的候选者都必须遵守几个标准。首先，电极不应与底层的亚1.0 nm栅电介质发生反应。其次，电极必须能够经受高温处理，以保持MOS器件的自对准结构，这已经成为当今先进技术的基础。最后，为了获得千兆级性能所需的阈值电压，电极必须提供特定的功函数，即NMOS器件需要功函数接近4 eV的栅极，而PMOS器件需要功函数接近5 eV的栅极。对两种不同金属的需求使工艺技术在材料和成本问题上都变得非常复杂。这个POWRE项目的目标是研究利用导电金属氧化物的功函数调制来形成纳米栅电极的替代方法。透明导电氧化物提供了通过改变化学成分来调节功函数的灵活性。这一特性可以用来造福纳米级的cmos。这项拟议活动背后的主要主题是在NMOS和PMOS区域的电介质上沉积单一的导电氧化层，然后通过非关键的掩蔽步骤，选择性地在N和P区域注入某些元素来调节功函数。这将消除两个单独的金属沉积步骤的需要，并极大地简化集成问题。此外，导电金属氧化物也可以提供优异的热稳定性和化学稳定性，这是以前从未考虑过的硅栅电极应用。如果上述建议的活动是可行的，即导电金属氧化物的功函数可以被调谐到与CMOS要求相匹配，那么这项工作为纳米级的CMOS进步提供了巨大的潜力。

0074800MisraTo obtain maximum performance from nanoscale CMOS devices, conventional polycrystalline silicon gate electrodes will have to be replaced by metallic layers. However, any replacement candidate for polysilicon must adhere to several criteria. Firstly, electrodes should not react with the underlying sub-1.0 nm gate dielectric. Secondly, the electrodes must be able to withstand high temperature processing in order to preserve the self-aligned structure of the MOS device, which has been the foundation of today's advanced technologies. Finally, to obtain desired threshold voltage for giga-scale performance, the electrodes must provide specific workfunctions, i.e. NMOS devices will require gates with workfunctions near 4 eV and PMOS devices will require gates with workfunctions near 5 eV. The need for two separate metals significantly complicates the process technology, both in material and cost issues.The goal of this POWRE project is to investigate alternate approaches for nano-gate electrode formation using workfunction modulation of conducting metal oxides. Transparent conducting oxides offer the flexibility of workfunction modulation via chemical composition changes. This property can be used to benefit nanoscale CMOS. The main theme behind this proposed activity is to deposit a single conducting oxide layer on both the NMOS and PMOS region dielectrics and then via non-critical masking steps, selectively implanting certain elements to modulate the workfunction on N and P regions. This would eliminate the need for two separate metal deposition steps and drastically simplify integration issues. Moreover, conducting metal oxides, never before considered for Si gate electrode applications, can also provide superior thermal and chemical stability. If the above proposed activities are feasible, i.e. workfunction of conducting metal oxides can be tuned in to match the CMOS requirements, then this work offers tremendous potential for nanoscale CMOS advancement.***