Si-Based Tunnel Diode Integration with CMOS and SiGe HBTs

本项目的目标是将硅基隧道二极管与CMOS和SiGe HBT技术集成，以展示具有更高电路速度、减少元件数量和降低功耗的电路，在半导体工业协会（SIA）的路线图上扩展CMOS而不减少线宽。拟议的项目将通过参与大学建立一个综合计划（特拉华州和罗切斯特理工学院）和政府研究实验室（海军研究实验室）的合作，目标是制造第一个硅基隧道二极管集成电路。本论文的研究将集中在硅基隧道二极管与CMOS和SiGe HBT技术相结合的简单隧道二极管电路上。这项工作将与另一个项目（NSF-ITR）同步进行，该项目涉及密歇根州、特拉华州、NRL和RIT，该项目提出研究由这种技术实现的新电路。这些工作包括：研究未金属化CMOS的后端热预算以承受隧道二极管处理;找到合适的清洗蚀刻剂，其为MBE过生长准备表面，同时对预先存在的CMOS是良性的;开发选择性蚀刻剂以去除CMOS顶部不需要的多晶MBE生长;在顶部源极/漏极注入物处将MBE过生长执行到预定义窗口中;检查隧道二极管过生长的可能发射极/基极结位移;研制选择性腐蚀剂，对HBT结构顶部的TD进行梅萨腐蚀，并实现一些简单的隧道二极管晶体管电路。硅基隧道二极管已经开发出来（NSF CAREER- Berger，DARPA- UltraElectronics），目前正在优化（NSF GOALI-Berger，NRL和Raytheon）。SiGe HBT集成将由特拉华州和NRL团队进行，他们在SiGe HBT的生长和制造方面具有丰富的经验。对于这个拟议中的项目，NRL的菲利普汤普森博士将执行MBE生长，特拉华州将执行隧道二极管和SiGe HBT的制造和测试，RIT将执行CMOS制造。特拉华州大学、海军研究院和罗切斯特理工学院之间的密切互动将促进公开讨论和对话。该提案旨在将电路设计师、半导体器件工程师和CMOS技术专家聚集在一起，以实现在aSi平台上实现隧道二极管/晶体管电路的唯一目的。本科研究和学生培训将发挥重要作用，在特拉华州通过现有的和预期的NSF REU补充和在RIT通过他们的学生运行CMOS工厂和RIT的高级论文项目。RIT的预算包括一名本科研究员。跨学科的工作和对NRL研究实验室的实地考察将加强教育过程。

The goal of this project is to integrate Si-based tunnel diodes with CMOS and SiGe HBTtechnology to demonstrate circuits which exhibit higher circuit speed, reducedcomponent count, and lowered power consumption, and which extend CMOS on theSemiconductor Industry Association (SIA) Roadmap without a linewidth reduction.The proposed project would establish an integrated program by involving universities(Delaware and Rochester Institute of Technology) and government research laboratories(Naval Research Laboratory) with the goal of making the first Si-based tunnel diodeintegrated circuit. The research will focus on simple tunnel diode circuits which combineSi-based tunnel diodes with CMOS and SiGe HBT technology. The work will besynergistic with another project (NSF-ITR) involving Michigan, Delaware, NRL and RITwhich proposes to study the new circuits enabled by this technology.This proposed project focuses upon developing integration recipes with CMOS andHBTs. This body of work includes: studying the back-end thermal budget forunmetalized CMOS to withstand tunnel diode processing; finding appropriate cleaningetchants which prepare the surface for MBE overgrowth while being benign to the pre-existingCMOS; develop selective etchants to remove unwanted poly-crystalline MBEgrowth atop the CMOS; perform MBE overgrowth into pre-defined windows atopsource/drain implants; examine possible emitter/base junction displacement with tunneldiode overgrowth; develop selective etchants to mesa etch the TD atop the HBTstructure; and realize some simple tunnel diode transistor circuits. The Si-based tunneldiodes have already been developed (NSF CAREER- Berger, DARPA- UltraElectronics) and are currently being optimized (NSF GOALI-Berger, NRL andRaytheon). SiGe HBT integration will be performed by Delaware and by the NRL team,who have considerable experience in the growth and fabrication of SiGe HBTs. For thisproposed project, Dr. Phillip Thompson at NRL will perform the MBE growths,Delaware will perform tunnel diode and SiGe HBT fabrication and testing, and RIT willperform the CMOS fabrication.Strong interaction between the University of Delaware, the Naval Research Laboratoryand Rochester Institute of Technology will foster open discussion and dialogue. Thisproposal seeks to bring together circuit designers, semiconductor device engineers andCMOS technologists for the sole purpose of realizing tunnel diode/transistor circuits on aSi platform. Undergraduate research and student training will play a significant role atDelaware through existing and anticipated NSF REU supplements and at RIT throughtheir student-run CMOS factory and RIT's senior thesis projects. RIT's budget includesan undergraduate researcher. The cross-disciplinary work and site visits to NRL researchlabs will enhance the educational process.