ITR: A CAD Framework for the Design and Optimization of Large-Scale Asynchronous Digital Systems

异步（或无时钟）电路已成为重新关注的焦点，因为它们有可能减轻下一代芯片设计中的一些挑战性问题：时钟分配，电源管理和设计重用。为了克服当前异步设计方法的局限性，该项目正在开发一个自动化的CAD框架，用于大规模异步系统的综合和优化。 除了基本的高级调度、绑定和分配以及硬件描述语言支持之外，（Verilog HDL），该项目正在探索开放和具有挑战性的问题：（a）高性能流水线综合和优化;（B）体系结构探索（针对频繁的常见情况操作）;（c）分布式控制器综合和优化;（d）系统级性能和功率分析;以及（e）混合异步/同步系统的合成。该工具框架正在应用于一些商业实例，并通过芯片设计、制造和测试进行验证。

Asynchronous (or clockless) circuits have become the focus of renewed interest because of their potential to alleviate a number of challenging problems in future-generation chip design: clock distribution, power management, and design reuse. To overcome the limitations of current asynchronous design methodologies, this project is developing an automated CAD framework for the synthesis and optimization of large-scale asynchronous systems. In addition to basic high-level scheduling, binding and allocation, and Hardware Description Language support (Verilog HDL), the project is exploring the open and challenging problems of: (a) high-performance pipeline synthesis and optimization; (b) architectural exploration (targeted to the frequent common-case operations); (c) distributed controller synthesis and optimization; (d) system-level performance and power analysis; and (e) the synthesis of mixed asynchronous/synchronous systems. The tool framework is being applied to a number of commercial examples and validated through chip design, fabrication, and test.