Giga-Scale System-On-A-Chip Design

该项目旨在建立一个研究千兆级系统芯片（SOC）设计的国际中心。​​该项目的重点是创新的设计方法、工具和算法，以实现在纳米技术中高效的千兆级SOC集成。研究活动包括调查和开发有效的SOC合成工具和方法，SOC验证，测试和诊断技术，以及SOC设计驱动程序，以激励和验证在本研究项目过程中开发的各种合成，验证和测试技术。设计驱动程序是网络处理器的SOC设计，其中包括嵌入式cpu、dps、fpga和各种存储器组件。SOC合成工具和方法的研究包括设计规范、设计划分、嵌入式dps和fpga的合成和优化、全芯片组装的物理合成以及设计重用的合成技术。验证与测试方面的研究主要集中在功能验证、片上可编程逻辑自检、模拟与混合信号自检、嵌入式存储器测试等方面。

This project is to establish an international center for research on giga-scale system-on-a-chip (SOC) designs. It involves researchers from U.S., Taiwan, and China. The center is being supported by the National Science Council (NSC) in Taiwan and the Chinese National Science Foundation (CNSF) to support the activities by researchers from Taiwan and China respectively.Focus of the project is on innovative design methodologies, tools, and algorithms that enable efficient giga-scale SOC integration in nanometer technologies. Research activities include investigation and development of efficient SOC synthesis tools and methodologies, SOC verification, test, and diagnostic technologies, and an SOC design driver that motivates and validates various synthesis, verification, and test techniques developed during the course of this research project. The design driver is a SOC design of a network processor, which includes embedded CPUs, DPSs, FPGAs, and various kinds of memory components. The research on SOC synthesis tools and methodologies includes design specification, design partitioning, synthesis and optimization for embedded DPSs and FPGAs, physical synthesis for full-chip assembly, and synthesis techniques for design re-use. The research on verification and test focuses functional verification, self-test using on-chip programmable logic, analog and mixed-signal self-test, and test for embedded memories.