Performance Driven Layout and Logic Synthesis

芯片复杂性的增加导致平均互连长度增加，并且互连所占的芯片面积比例越来越大。本文提出了几个与亚微米技术互连相关的问题，我们将集中讨论RC互连中的同时开关串扰噪声效应。我们的目标是在存在串扰的情况下，开发有效的，易于计算和准确的延迟界限，并表征和防止传播串扰信号。除了校正串扰引起的问题，我们还将开发在串扰存在下的电路优化方法。我们将开发尺寸调整工具、缓冲区插入、间距和网络重新排序，这些工具将考虑串扰和延迟。同时，我们将探索布尔级的规律性，以实现大多数局部互连的布局。其最终目标是发展一种逻辑综合方法，这种方法可以产生高度规则的布局结构，而不需要大面积的代价。我们建议继续我们的工作，波引导设计方法，我们将开发工具，逻辑综合和物理设计这样的电路。

The increased chip complexity causes that average interconnect lengths increase and proportionallylarger and larger fraction of chip's area is occupied by interconnects. This proposal addresses several is-suesrelated to interconnects in submicron technologies.We will concentrate on simultaneous switching cross-talk noise effects in RC interconnects. Our goalhere is to develop efficient, easy to compute and accurate bounds on delay in the presence of crosstalk andto characterize and prevent propagating crosstalk signals. Besides correcting the crosstalk caused prob-lemswe will also develop methodologies of circuit optimization in the presence of crosstalk. We will developgate sizing tool, buffer insertion, spacing and net reordering which will consider both cross-talk and delay.At the same time we will explore regularity at the Boolean level to achieve layouts with mostly localinterconnects. The ultimate goal is to develop logic synthesis methodology which would produce highly reg-ular layout structures without large area penalty. We propose to continue our work on wave steered design methodology and we will develop tools for logic synthesis and physical design of such circuits.