CAREER: Career Development Plan: Behavioral Modeling, Simulation and Optimization for Mixed-Signal System on a Chip

提案编号：0448534博士。加州大学河滨分校的谭向东（Sheldon Tan）这项研究旨在开发一个关于行为建模、仿真和优化技术的综合研究和教育计划，以解决和克服混合信号（MS）片上系统（SoC）的设计挑战，并实现向新一代混合信号VLSI系统的飞跃。重点是开发高效的MS soc设计建模、仿真和优化技术，MS soc设计包括模拟和数字模块，并在混合频率范围（基带频率或射频（RF））下工作。该项目特别针对(a)基于基于图的线性和非线性模拟电路方法的有效参数行为建模和分层分段线性（PWL）非线性建模技术的发展；(b)研究基于建模技术优化MS-SoC电路的模拟电路和片上供电系统的有效算法。新的建模技术将探索一种基于决定性设计图（DDD）的符号分析方法，以构建考虑设备参数范围和设计变化的行为模型，以应对日益增加的制造不确定性。对于非线性模拟电路的建模，将研究基于ddd的分层分段线性（PWL）建模技术，该技术有望在各种抽象层次上对非常大的非线性电路进行高保真的行为建模。随着越来越多的物理效应变得突出，设计实践，特别是模拟电路，已经成为一个类似于优化的过程，因为性能、可靠性和可制造性规范必须同时得到满足或优化。这种类似优化的设计范式需要新的不同于数字电路的设计策略和方法，本研究将对此进行探索。该计划的教育部分包括开发新的MS soc行为建模，仿真和优化课程，以及通过网络教学工具和面向项目的学习探索创新的学习方法，以培养具有混合信号soc行为建模，设计和验证知识的未来工程师。本研究项目将培养精通MS VLSI设计和MS CAD开发的工程师。

AbstractNSF Proposal#: 0448534Dr. Xiang-Dong (Sheldon Tan) TanUniversity of California at RiversideThis research seeks to develop an integrated research and education program on behavioral modeling, simulation, and optimization techniques to address and overcome the mixed-signal (MS) system-on-a-chip (SoC) design challenges and enable a leap to a new generation of mixed-signal VLSI systems. The focus is to develop efficient techniques for modeling, simulation and optimization of MS SoCs designs, which consist of both analog and digital blocks and operates in mixed frequency ranges (base-band frequency or radio frequency (RF)). The project specifically targets at (a) development of efficient parametric behavioral modeling and hierarchical piecewise linear (PWL) nonlinear modeling techniques based on a graph-based approach for linear and nonlinear analog circuits; (b) investigation of efficient algorithms for optimizing analog circuits and on-chip power-delivery systems for MS-SoC circuits based on modeling techniques. The new modeling techniques will explore a determinant-design diagram (DDD) based symbolic analysis method to construct behavioral models that consider device parameter ranges and design variations to cope with increasing manufacture uncertainty. For modeling nonlinear analog circuits, DDD-based hierarchical piece wise linear (PWL) modeling techniques will be investigated, which promises high fidelity behavioral modeling of very large nonlinear circuits at various abstract levels. As more physical effects become prominent, design practice, especially for the analog circuits, has become an optimization-like process because performance, reliability and manufacturability specifications have to be satisfied or optimized simultaneously. Such optimization-like design paradigms require new different design strategies and methodologies from that of digital circuits and will be explored in this research.The education component of the program consists of development of new curriculum in behavioral modeling, simulation and optimization of MS SoCs, and exploration of innovative learning approaches via web-enabled instructional tools and project-oriented learning for the education of future engineers with the knowledge of behavioral modeling, design and verification for mixed-signal SoCs. Engineers very versed in MS VLSI design and MS CAD development will be trained under this research project.