NIRT: (Nanoscale Devices and System Architecture): Fault-tolerant, Probalisitic Computing with Markov Random Field Architectures and CMOS Nanodevices
NIRT: (Nanoscale Devices and System Architecture): Fault-tolerant, Probalisitic Computing with Markov Random Field Architectures and CMOS Nanodevices
批准号:
0506732
负责人:
Ruth Bahar
金额:
$31.42万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2005
资助国家:
美国
项目状态:
已结题
起止时间:
2005-09-01 至 2010-08-31
中文摘要
NIRT:容错,概率计算与马尔可夫随机场体系结构和CMOS纳米器件摘要该项目研究概率设计方法的计算机体系结构的基础上马尔可夫随机场(MRF)。 MRF方法可以模拟任意数字电路,其逻辑运算产生于相邻电路节点的相互作用。 计算通过状态在电路中的概率传播进行,输入和输出被平等对待。 这种方法在处理纳米级时可能特别合适,因为它们容易受到高水平噪声的影响。 MRF逻辑可以在修改的基于CMOS的电路中实现,该电路使用输出-输入反馈来最大化正确逻辑状态的联合概率,权衡电路面积和速度以获得关键的容错性和抗噪性。这项研究将映射到CMOS的概率MRF设计方法,从单个器件和小型组合和时序逻辑测试电路,通过更高层次的架构设计。 面对噪声裕度、工艺可变性和制造公差的降低,高端计算架构将越来越多地必须处理可靠性和鲁棒性问题。在这个项目中遵循的概率设计方法学研究一个方向,以扩展硅数字逻辑超出基本物理约束对标准设计的限制。
英文摘要
NIRT: Fault-tolerant, Probabilistic Computing with Markov Random Field Architectures and CMOS NanodevicesAbstractThe project examines probabilistic design methodologies for computer architectures based on Markov random fields (MRF). The MRF approach can model arbitrary digital circuits with logic operation arising from the interaction of neighboring circuit nodes. The computation proceeds via probabilistic propagation of states through the circuit, with inputs and outputs treated on an equal footing. This approach may be particularly appropriate when dealing with the nanoscale since they are susceptible to high levels of noise. The MRF logic can be implemented in modified CMOS-based circuitry that uses output-input feedback to maximize the joint probability of correct logic states, trading off circuit area and speed for crucial fault tolerance and noise immunity. The research will map a probabilistic MRF design methodology onto CMOS, proceeding from individual devices and small combinational and sequential logic test circuits, through to higher-level architectural designs. High-end computing architectures will increasingly have to deal with issues of reliability and robustness, in the face of reduced noise margins, process variability, and manufacturing tolerances. The probabilistic design methodology being followed in this project investigates one direction to extend silicon digital logic beyond the limits imposed on standard designs by fundamental physical constraints.
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