CMOS VLSI Design of Low Power Scalable Heterogeneous Networks for Multi-Core Systems-on-Chip

提案编号：0541278.Luca CarLoniKenneth Shepard(co-PI)哥伦比亚大学标题：CMOSI片上多核系统的低功耗可扩展异质网络的VLSI设计在过去十年中，通过对千兆级集成的延迟、能量消耗、信号完整性和设计生产率施加主要限制，互连已经取代晶体管成为集成电路性能的主要决定因素。用于通信的低延迟、低能量电路将需要规则、结构化的互连来设计线路并将电路调谐到这些线路。片上网络(OCN)提供了这样的结构化结构，其中通信是通过通过通用互连结构而不是使用由CAD工具路由的特定于设计的全局布线网络来路由分组来获得的。PIS将研究用于多核系统片上系统的可扩展OCN的设计，方法是将基于衰减补偿的新的低延迟、低能量、电流模式信令方法与延迟不敏感通信协议的设计相结合，以支持容错通信以及内核的动态电压和频率调节和掉电。

Proposal no: 0541278.Luca CarloniKenneth Shepard (co-PI)Columbia UniversityTitle: CMOS VLSI Design of Low-Power Scalable Heterogeneous Networks for Multi-Core Systems-on-Chip.During the past decade, interconnects have replaced transistors as the dominant determiner of integrated circuit performance by imposing primary limits on latency, energy dissipation, signal integrity and design productivity for giga-scale integration. Low-latency, low-energy circuits for communications will require regular, structured interconnect to engineer wires and tune circuits to those wires. On-chip networks (OCN)provide such a structured fabric in which communication is obtained by routing packets through a general-purpose interconnect structure rather than using a design-specific ad hoc global wiring network routed by CAD tools. The PIs will investigate the design of scalable OCNs for multi-core systems-on-chip by combining a new low-latency, low-energy, current-mode signalling approach based on damping compensation with the design of latency-insensitive communication protocols extended to support fault-tolerant communication as well as dynamic voltage and frequency scaling and power-down for the cores.