Hybrid Clock Networks using Distortionless Transmission Lines

摘要0618163 PI：Chung-Kuan ChengCSE部门，加州大学圣地亚哥分校标题：采用无失真传输线的混合时钟网络随着VLSI技术的发展，互连线延迟对系统性能起着决定性的作用，因此互连线延迟的变化变得越来越重要。工艺、电压和温度变化会对互连延迟产生显著影响。因此，互连设计的鲁棒性非常重要。在最近的一项发明中，Cheng的团队设计了一种无失真传输线，与传统线路相比，该传输线在实现光速的同时，功耗降低了85%或更多。本计画将探讨整合无失真传输线与互连拓扑、电路型式及电磁波技术于混合网路之应用。探索可以导致光速，极低功耗和低抖动时钟分布的设计。SGER是这个探索性和高回报项目的最佳手段，因为资金可以及时获得。

Abstract0618163PI: Chung-Kuan ChengCSE Dept., UC, San DiegoTitle: Hybrid Clock Networks Using Distortionless Transmission LinesWith the advance of the VLSI technology, the variation of interconnect delay is becoming critical since interconnect delay plays a dominant role in system performance. Process, voltage, and temperature variations can have significant effects on interconnect delay. Therefore, the robustness of interconnect design is important. This is especially crucial for clock distributions because the delay variations contribute to clock jitters and skews.In a recent invention, Cheng's group devised a distortionless transmission line which achieves the speed of light at an 85% or greater reduction in power consumption over traditional wires. The proposed project explores the utilization of the distortionless transmission line integrated with the interconnect topologies, circuit styles, and electromagnetic wave techniques into a hybrid network. The exploration can lead to the design of the speed of light, extremely low power, and low jitter clock distributions. The SGER is the best means for this exploratory and high return project because of the availability of the funding in a timely manner.