Efficient Probabilistic Correction of Noise-Induced Errors in Encoded Signal Processing Algorithms

由于技术的缩放和超深亚微米（UDSM）电路对噪声（降低噪声裕度）和软误差（由大气中子引起）引起的不确定性的敏感性增加，因此有必要在未来的逻辑设计中设计误差检测和校正能力，以实现可靠的计算。过去，数据编码技术主要用于有线和无线通信信道的错误检测和纠错。为了在未来的纳米级技术中实现可靠的计算，不仅需要对数据进行编码，而且需要对数据上执行的计算进行编码，以便进行实时错误检测和纠正（即需要执行冗余计算）。预计从1992年到2011年，规模化技术中组合逻辑的错误率将上升9个数量级，与“无保护”存储元件的错误率相当。目前，编码技术被用于设计可靠的存储库和实现可靠的存储访问，但它们在片上信号处理中的应用受到限制。在可靠的片上计算中广泛使用编码技术的主要障碍之一是实现具有单位和多位错误的逻辑错误检测和纠正能力的编码技术所需的数据成本和电路冗余。虽然在大多数已知的基于算法和通信系统的编码技术中，错误检测相对容易完成，但错误纠正是一个更难的问题，并且可能需要大量的计算来精确地进行错误纠正。这使得在不损失显著吞吐量的情况下实现实时校正变得困难，如果不是不可能的话，对于大多数涉及矩阵向量乘法的DSP应用来说尤其如此，并且是本提案的核心主题。在这种情况下，重要的是要指出，在未来具有高错误率的规模化技术中，对吞吐量影响最小的快速纠错将是关键的技术支持因素。如果没有这种能力，由于电路和系统级性能的总体损失，技术扩展本身可能会陷入停顿。本研究主要关注片上线性和非线性数字信号处理计算的编码和概率校正技术，这些技术允许在对电路性能和功耗影响最小的情况下执行近乎精确的校正，这些系统由不可靠的组件组成，这些组件在输出线上产生间歇性错误，错误率远高于精确的误差校正技术，而不会造成显著的性能损失错误率的增加被认为是由非常激进的技术扩展问题驱动的。这些误差是由于UDSM电路中的噪声边界减小、电源/地面反弹和辐射引起的影响，或者是由于实时刺激间歇激发的内部信号线的永久故障（卡在0/卡在1）。此外，所提出的技术也可以应用于特殊类别的模拟电路（滤波器、放大器等）。预计所提出的研究将为解决使用不可靠硬件进行可靠计算的挑战（高错误率）开辟新的途径，这一问题预计将在未来十年主导可靠计算领域。

Due to technology scaling and the increased susceptibility of ultra deep submicron (UDSM) circuitry to uncertainties originating from noise (reduced noise margins) and soft errors (induced by atmospheric neutrons), it will become necessary to design error detection and correction capability into future logic designs for reliable computation. In the past, data encoding techniques have mostly been used for error detection and correction in wired and wireless communications channels. In order to enable reliable computing in nanoscale technologies of the future, not only data but also computation performed on the data will need to be encoded for real-time error detection and correction (i.e. redundant computations will need to be performed). It is expected that error rates of combinational logic in scaled technologies will escalate by 9 orders of magnitude from 1992 to 2011, when it will equal the error rate of "unprotected" memory elements. Currently, coding techniques are used to design reliable memory banks and enable reliable memory access, but their use in on-chip signal processing has been limited. One of the key barriers to widespread use of coding techniques for reliable on-chip computing is the cost of data and circuit redundancy necessary to implement a coding technique with logic error detection and correction capabilities for single and multiple bit-errors. While error detection is accomplished relatively easily across the majority of known algorithm-based and communication systems coding techniques, error correction is a harder problem and can require significant computation for exact error correction. This renders real-time correction without loss of significant throughput difficult, if not impossible, to achieve and is especially true for the majority of DSP applications that involve matrix-vector multiplications and are the core subject of this proposal. In this context, it is important to point out that in future scaled technologies with high error rates, rapid error correction with least impact on throughput will be a critical technology enabling factor. Without this capability, technology scaling itself may grind to a halt due to gross loss of circuit and system level performance.This research focuses primarily on coding and probabilistic correction techniques for on-chip linear and non-linear digital signal processing computations that allow near-exact correction to be performed with minimal impact on circuit performance and power consumption in systems composed of unreliable components that generate intermittent errors on their output lines at much higher error rates than can be handled by exact error correction techniques without significant loss of performance The increased error rate is assumed to be driven by very aggressive technology scaling issues. The errors are due to reduced noise margins in UDSM circuitry, power/ground bounce and radiation-induced effects or due to permanent failures (stuck-at-0/stuck-at-1) on internal signal lines that are excited intermittently by real-time stimulus. In addition, the proposed techniques can be applied to special classes of analog circuits as well (filters, amplifiers, etc). . It is expected that the proposed research will open up new avenues for addressing the challenges of performing reliable computation with unreliable hardware (high error rates), a problem that is expected to dominate the field of reliable computing in the coming decade.