Low Temperature Plasma Etching of Copper to Minimize Size Effects in Sub-100 nm Features

集成电路（IC）的复杂性的增加已经产生了逐步增强的能力，性能和可靠性，而每个功能的IC成本不断下降。这些成就对用于连接同时制造的数百万个晶体管的互连密度提出了严格的要求。为了满足当前和未来几代集成电路的速度要求，铜（Cu）实际上已经取代了铝作为互连材料。由于无法在180℃以下的温度下开发出有效的减等离子体蚀刻工艺，因此采用了damascene技术对Cu薄膜进行刻蚀。在这里，通过在等离子体蚀刻的电介质沟槽中电镀Cu来避免Cu的减法蚀刻。然后使用化学机械平面化（CMP）去除覆盖在沟槽和电介质上方的Cu，从而产生Cu图案。不幸的是，当横向尺寸减小到100nm以下时，电镀Cu的电阻率迅速增加；电阻率中的这种“尺寸效应”是IC行业未来器件一代的关键限制，因为它降低了电路速度，并可能对本地互连的可靠性产生不利影响。此外，CMP过程的控制及其对环境和经济的影响也是有问题的。知识价值：该项目的知识价值包括开发一种新的低温铜蚀刻工艺，该工艺将有助于改进铜互连设计，提高效率，提高速度并降低功耗。热力学分析表明，铜可能通过两步过程蚀刻：等离子体氯化铜表面，然后用H2等离子体形成和解吸Cu3Cl3。初步结果表明，使用这种方法可以在室温下蚀刻Cu，因此表明在低温下等离子体蚀刻/图案Cu薄膜的过程是可能的。这项研究将使集成电路产业克服阻碍半导体技术进步的主要问题和限制。这项工作将对铜图案的两步等离子体工艺有一个基本的了解，并将进行初步的图案定义研究，以评估各向异性蚀刻图案的能力，从而评估大规模集成电路制造的潜力。该项目是化学工程研究生的理想选择，因为它将实验研究与基础热力学和动力学研究相结合，以解决一个关键的工业问题。更广泛的影响项目的更广泛的影响包括：(1)减轻Cu互连中的尺寸效应，从而消除目前存在的IC技术进步的限制；(2)开发一种更环保、成本更低、更有效的Cu薄膜图图化方法；(3)提供有关Cu低温蚀刻控制步骤的分子水平信息；(4)为本科生和研究生的ChBE课程开发新的示例和案例研究。(5)每年夏天教育/培训参加佐治亚理工学院夏季本科生工程研究（SURE）项目的少数民族本科生和高中生；(6)通过佐治亚理工学院的国家纳米技术基础设施网络（NNIN）站点和PI？S在当地高中的私人关系。

CBET-0755607HessThe increased complexity of integrated circuits (ICs) has yielded progressively enhanced capabilities, performance and reliability, while the IC cost per function has dropped continuously. These accomplishments have placed severe requirements on the density of interconnects used to connect the millions of transistors manufactured simultaneously. In order to meet the speed requirements for current and future generations of ICs, copper (Cu) has virtually replaced aluminum as the interconnect material. Because of an inability to develop an effective subtractive plasma-based etch process for Cu at temperatures below 180oC, damascene technology is used to pattern Cu films. Here, subtractive etching of Cu is avoided by electroplating Cu into plasma-etched dielectric trenches. Chemical mechanical planarization (CMP) is then used to remove the Cu overcoated above the trenches and dielectric, thereby creating Cu patterns. Unfortunately, the electrical resistivity of electroplated Cu increases rapidly as lateral dimensions are reduced below 100 nm; this "size effect" in electrical resistivity is a critical limitation to future device generations in the IC industry since it reduces circuit speed and can have an adverse effect on the reliability of local interconnects. In addition, control of the CMP process as well as its environmental and economic impact, are problematic. Intellectual Merit:The intellectual merit of the project involves the development of a novel low temperature Cu etch process that will facilitate improved Cu interconnect designs with higher efficiencies, enhanced speed and reduced power consumption. Thermodynamic analyses have suggested that Cu might be etched by using a two-step process: plasma chlorination of Cu surfaces followed by formation and desorption of Cu3Cl3 using a H2 plasma. Preliminary results have demonstrated the ability to etch Cu below room temperature using this approach and thus suggest that a process to plasma etch/pattern Cu films at low temperatures is possible. This research will allow the IC industry to overcome a major problem and limitation impeding the advance of semiconductor technology. This work will develop a fundamental understanding of the proposed two-step plasma process for Cu patterning and will perform preliminary pattern definition studies to evaluate the ability to anisotropically etch patterns and thus assess the potential for large scale IC manufacture. The project is ideal for chemical engineering graduate students in that experimental studies are combined with fundamental thermodynamics and kinetics investigations to address a critical industrial problem. Broader ImpactThe broader impacts of the project include: (1) mitigate size effects in Cu interconnects thereby removing a limitation currently existing for the advancement of IC technology, (2) develop a more environmentally benign, lower cost, effective method of patterning Cu films, (3) provide molecular level information regarding the controlling steps in low temperature etching of Cu, (4) develop novel examples and case studies for undergraduate and graduate ChBE courses, (5) educate/train minority undergraduate and high school students each summer who participate in the Georgia Tech Summer Undergraduate Research in Engineering (SURE) Program at Georgia Tech, (6) educate high school students and teachers in IC fabrication and environmental issues through the National Nanotechnology Infrastructure Network (NNIN) site at Georgia Tech and through the PI?s personal contacts in local high schools.