Carrier Transport in Scaled Charge-Trap NVSM and CMOS Devices

摘要规模电荷陷阱非易失性半导体存储器(NVSM)和CMOS器件中的载流子输运研究计划的目的是研究规模电荷陷阱非易失性半导体存储器(NVSM)和CMOS器件。我们的研究将集中在两种异质绝缘器件结构上：(1)金属和多晶硅栅极、高K、在高K介质中具有固定电荷的纳米级CMOS晶体管和(2)具有可编程电荷存储功能的非易失性、电荷陷阱、纳米级SINOS半导体存储器件。特别是，我们将着重于高温区CMOS器件中载流子迁移率的远距离库仑和表面粗糙度散射、电荷输运和陷阱以及栅漏的量子力学建模和实验表征。电荷陷阱NVSM器件是类SINOS结构，其栅电介质由隧道氧化物(O)、存储氮化硅(N)和覆盖的高K阻挡氧化物(I)组成，作为氧化铝和/或二氧化HfnO2以增加薄膜的介电常数。我们将制作和模拟实验规模的5V SiNOS器件，重点放在写入/擦除、保持和耐久性上，并研究氮化物中存储电荷对载流子迁移率的影响。我们开发了一种通过双端C-V和G-V测量来提取低场载流子迁移率的新技术，从而实现了异质绝缘栅介质的优化。SINOS器件提供了一个独特的机会，可以将电荷放置在硅-二氧化硅界面附近，并探索它们对载流子迁移率的影响。我们将研究这些器件中的1/f和RTS噪声，重点是通过考虑囚禁和自由电荷涨落来统一现有的理论。我们将通过对薄膜厚度和成分的材料测量来补充电学表征，特别是在使用原子层沉积(ALD)方面。此外，我们将使用高分辨率透射电子显微镜(HRTEM)和角度分辨X射线光谱分析(ARXP)来研究薄膜厚度和结构特性及其与理论模型的关系。其智力优势依赖于研究和教育的结合，以探索电荷陷阱NVSM和高K纳米级CMOS器件中的低场、载流子输运，以及迁移率退化、电荷陷阱、栅漏、低频RTS和1/f噪声的量子力学处理。我们用简单的两端电导/电容测量来检查迁移率，以最大限度地减少制造具有欧姆接触的完整三端器件的需要，直到在实验中确定了优化的栅堆叠为止。NVSM器件提供了一种独特的方法来在Si-SiO_2界面附近电定位和定位电荷中心，以研究它们对载流子传输和存储以及栅漏和低频噪声的影响。我们的理论和实验研究将得到材料参数变化的补充，并使用先进的材料表征技术和HRTEM和ARXPS来模拟纳米级的NVSM和CMOS器件。我们计划中更广泛的方面将促进纳米电子劳动力的多样性，并提供智力技术转让、研究和教育的整合，以及促进与经济中的工业部门的伙伴关系。我们开发了优秀的教育和推广计划，以增加纳米电子领域的多样性和机会，特别是硅半导体器件，这是保持美国领先地位并为全球硅基半导体行业的毕业生提供就业机会的重要领域。我们的研究为少数族裔学生的外展、实习和与业界的伙伴关系提供了一个极好的工具。我们研究的变革性本质在于：(1)通过交替的高K薄膜来获得低电压、低功耗的NVSM，以保持势垒高度，同时提高介电常数，(2)新的量子力学1/f噪声模型，以及(3)利用简单的双端C-V和G-V结构来模拟低场输运的新方法，该方法无需大量的光刻设备即可制造。这一概念适用于广泛的新兴纳米级器件(不一定是硅)中载流子传输的研究，并将有助于半导体技术领域的快速和创新进步。

AbstractCarrier Transport in Scaled Charge-Trap NVSM and CMOS DevicesThe objective of the proposed research program is to study scaled charge-trap nonvolatile semiconductor memory (NVSM) and CMOS devices. Our study will focus on two hetero-insulator device structures: (1) metal and polysilicon gate, high-K, nanoscaled CMOS transistors with fixed charge in the high-K dielectric and (2) a nonvolatile, charge-trap, nanoscaled SINOS semiconductor memory device with programmable charge storage. In particular, we will focus on the quantum mechanical modeling and experimental characterization of carrier mobility degradation due to remote Coulomb and surface roughness scattering, charge transport and trapping and gate leakage in high-K CMOS devices. The charge trap NVSM devices are SINOSlike structures with a gate dielectric comprised of a tunnel oxide (O), a storage silicon nitride (N), and an overlying high-K blocking oxide (I) as aluminum oxide and/or hafnium dioxide to increase the dielectric constant of the film. We will fabricate and model experimental scaled 5V SINOS devices with an emphasis on Write/Erase, Retention and Endurance and study the influence of stored charge in the nitride on the carrier mobility. We have developed a novel technique to extract the low-field carrier mobility with a two-terminal C-V and G-V measurement to permit the optimization of the hetero-insulator gate dielectric. The SINOS devices offer a unique opportunity to electrically place charge near the Si-SiO2 interface and to explore their influence on carrier mobility. We will examine 1/f and RTS noise in these devices with a focus on unifying existing theories through a consideration of both trapped and free charge fluctuations. We will complement the electrical characterization with material measurements on film thicknesses and compositions, especially in the use of atomic layer deposition (ALD). In addition, we will employ high-resolution transmission electron microcopy (HRTEM) and angle-resolved X-ray photo spectroscopy (ARXP) to study film thickness and structural properties and their relation to theoretical models.The intellectual merit relies on an integration of research and education to explore low-field, carrier transport in charge-trap NVSM and high-K nanoscaled CMOS devices with a quantum mechanical treatment of mobility degradation, charge trapping, gate leakage, and low-frequency RTS and 1/f noise. We examine mobility with a simple two-terminal conductance/capacitance measurement to minimize the need to fabricate complete three-terminal devices with ohmic contacts until an optimized gate stack has been determined in the experiments. NVSM devices offer a unique approach to electrically locate and position charge centers in the vicinity of the Si-SiO2 interface to study their influence on carrier transport and storage as well as gate leakage and low-frequency noise. Our theoretical and experimental studies will be complemented with a variation of material parameters and the use of advanced materials characterization techniques with HRTEM and ARXPS to model nanoscaled NVSM and CMOS devices. The broader aspects in our program will advance diversity in the nanoelectronics workforce and provide intellectual technology transfer, integration of research and education, and promotion of partnerships with the industrial sector of the economy. We have developed excellent educational and outreach programs to increase diversity with opportunities in nanoelectronics, especially silicon semiconductor devices an important area to maintain US leadership and provide jobs for graduates in a global silicon-based semiconductor industry. Our research offers an excellent vehicle for minority student outreach, internships, and partnerships with industry. The transformative nature of our research lies in (1) a new approach to obtain low voltage, low power dissipation NVSMs with alternate high-K films to maintain barrier height while increasing the dielectric constant, (2) a new, quantum mechanical 1/f noise model, and (3) a novel method to model low field transport with simple two-terminal C-V and G-V structures, which is easily fabricated without extensive photolithographic equipment. The concept is applicable to the study of carrier transport in a broad range of emerging nanoscaled devices, not necessarily silicon, and will aid rapid and innovative advances in the field of semiconductor technology.