SHF:Small:Designing Low-Latency and Robust Interconnection Networks with Fine-Grain Dynamic Adaptivity Using Asynchronous Techniques

复杂的、不同种类的数字系统的组织成为下一个十年乃至更长时间的基础研究问题之一。最近一个很有希望的策略是使用结构化通信，以互连网络或片上网络(NOC)的形式。这种NoC最近被用于许多系统中，从用于消费类应用的嵌入式片上系统到用于高端并行处理器的存储器接口。同步(即时钟)NoC的设计和能力已经取得了许多进展，但支持设计重用、混合时钟域以及动态电压和频率调节(DVFS，以提高系统功率)的需求日益增加，这突显了单时钟框架固有的刚性。虽然已经开发了许多异步和全局异步局部同步(GALS)NoC，并在某些成本指标上显示出优势，但大多数具有重大的性能和面积开销，在一系列关键应用中不具竞争力，而其他旨在实现高性能的NoC则需要使用先进的电路技术。该建议旨在弥补这一差距，开发主要使用标准硬件组件的中高端异步/GALS NoC，与同类单时钟设计相比，其成本指标显著改善：动态功率、系统延迟、吞吐量、面积和可靠性。该方法的一个新奇之处将是探索在单个路由器节点级别使用细粒度动态自适应，其中节点可以根据观察到的环境流量重新配置自己，以在延迟、吞吐量和静态功率方面进行“清理”改进。将直接与最先进的计时系统进行比较，使用一种有前景的多同步方法(具有单一时钟速率，但允许相位失调，称为“中间同步”)。还将开发详细的模拟和综合工具以及支持流程。拟议框架的更广泛影响将是在克服关键系统瓶颈方面为异步设计的竞争生存能力提供新的进步水平。预计这项工作将通过使用异步性，在推动组织复杂系统的范式转变方面发挥作用。预计这一结果还将在设计下一代国家石油公司方面取得重大进展。

The organization of complex heterogeneous digital systems looms as one of the fundamental research problems of the next decade and beyond. One recent promising strategy is the use of structured communication, in the form of interconnection networks or networks-on-chip (NoCs). Such NoCs have been recently used in many systems, ranging from embedded systems-on-chip for consumer applications to memory interfaces for high-end parallel processors. A number of advances have been made in the design and capabilities of synchronous (i.e. clocked) NoCs, but the increased need to support design reuse, mixed clock domains, and dynamic voltage and frequency scaling (DVFS, to improve system power), have highlighted the inherent rigidity of a single-clock framework. While a number of asynchronous and globally-asynchronous locally-synchronous (GALS) NoCs have been developed, and demonstrated benefits in some cost metrics, most have major performance and area overheads and are not competitive for a range of critical applications, while others aiming at high performance require the use of advanced circuit techniques. This proposal aims to bridge the gap, developing medium- to high-end asynchronous/GALS NoCs, using mostly standard hardware components, with significantly improved cost metrics over comparable single-clock designs: dynamic power, system latency, throughput, area and reliability. A novelty of the approach will be to explore the use of fine-grain dynamic adaptivity, at the individual router node level, where, opportunistically, nodes can reconfigure themselves to ``scavenge'' improvements in latency, throughput and static power, based on observed ambient traffic. A direct comparison will be made with state-of-the-art clocked systems, using a promising multi-synchronous approach (with a single clock rate, but tolerating phase misalignment, called ``mesochronous''). Detailed simulation and synthesis tools and support flows will also be developed.The broader impact of the proposed framework will be to provide a new level of advancement for the competitive viability of asynchronous design in overcoming key system bottlenecks. It is anticipated that this work will play a role in advancing a paradigm shift in organizing complex systems, through use of asynchrony. The results are also expected to provide a major advance in designing next-generation NoCs.