SHF: Small: Parasitics-aware Exploration of the FinFET SRAM Design Space

随着FinFET(一种场效应晶体管或FET)在22 nm技术节点和更远的技术节点的采用，平面互补金属氧化物半导体(CMOS)技术的扩展即将结束。由于鳍体周围包裹着多个栅极，FinFET显示出更好的沟道电势控制和缩放，从而缓解了平面短沟道器件面临的爆炸性泄漏电流问题。由于静态随机存取存储器(SRAM)位单元通常是集成电路上最密集的特征，研究人员已经开始研究FinFET SRAM的设计和可制造性。这些研究大多集中在增强/对比静态随机存取存储器直流(DC)指标。然而，这样的指标对FinFET位单元设计者来说并不是一个准确的指南，因为两个拓扑等效位单元的寄生电容可能会非常不同(由于鳍片间距等不同)，从而导致非常不同的暂态特性。因此，为了通过仿真来预测阵列尺度的度量，准确地捕获瞬时行为是绝对必要的。为了实现后者，需要从版图中准确地提取SRAM寄生电容。使用首席研究员(PI)小组开发的精确寄生电容提取方法，该项目计划从直流指标和暂态行为的角度，在工艺-电压-温度变化的情况下探索FinFET SRAM设计空间。由于SRAM占现代微处理器面积的50%以上，因此以最好的SRAM位单元设计为基础是非常重要的。因此，这项工作的成功完成应该对半导体行业非常有利。将通过网络传播将要开发的设计/方法/工具。技术转让将通过与PI互动的各种公司进行。这些材料将包括在PI教授的一门关于纳米技术设计的课程中。普林斯顿大学有本科生独立研究的传统。预计许多高年级学生都会在这个主题上做研究项目。女性和少数族裔学生将通过普林斯顿的总统奖学金计划被吸引到这项研究中。到目前为止，PI已经指导了10名女性博士生。还计划为高中生开展进一步的外展活动。在过去的两年里，PI监督了四名高中生的研究，其中包括一名女学生。

Planar complementary metal-oxide-semiconductor (CMOS) technology scaling is coming to an end with the adoption of FinFETs (a type of field-effect transistor or FET) at the 22nm technology node and beyond. As a result of having multiple gates wrapped around the fin body, FinFETs exhibit better control of the channel potential with scaling, thereby alleviating the explosive leakage current problem faced by planar short-channel devices. Since static random access memory (SRAM) bit-cells are often the densest features patterned on an integrated circuit, researchers have begun investigating the design and manufacturability of FinFET SRAMs. Most of these investigations focus on enhancing/contrasting SRAM direct current (DC) metric targets. However, such metrics are not an accurate guide to FinFET bit-cell designers, as parasitic capacitances for two topologically equivalent bit-cells can be very different (due to differing fin pitches, etc.), resulting in widely varying transient characteristics. Thus, in order to predict array-scale metrics through simulation, capturing transient behavior accurately is absolutely essential. To accomplish the latter, SRAM parasitic capacitances need to be extracted accurately from the layout. Using an accurate parasitic capacitance extraction method that the principal investigator's (PI's) group has developed, the project plans to explore the FinFET SRAM design space from both DC metrics and transient behavior points of view, under process-voltage-temperature variations. Since SRAMs account for more than 50% of the area of modern microprocessors, it is very important to base them on the best SRAM bit-cell design. A successful conclusion of this work, hence, should be very beneficial to the semiconductor industry. The designs/methodologies/tools that are to be developed will be disseminated through the web. Technology transfer will be done through various companies the PI interacts with. The material will be included in a course on Design with Nanotechnologies that the PI teaches. Princeton has a tradition of undergraduate independent research. Many seniors are expected to do their research project on this topic. Female and minority students will be attracted to this research through Princeton's Presidential Fellowship Program. The PI has supervised 10 female Ph.D. students so far. Further outreach activities are also planned for high-school students. The PI has supervised the research of four high-school students in the last two years, including a female student.