SHF: Small: Efficient CPU-GPU Communication for Heterogeneous Architectures

未来的芯片多处理器（CMP）将有硅空间和技术，以纳入数百个核心。趋势是在单个平台上集成数十个核心和硬件加速器（HA），例如GPU。拟议的异构架构将使未来的芯片能够在其功率预算内运行，同时提供大型科学应用所需的每瓦高吞吐量。世界500强超级计算机中的许多都将数千个CPU与GPU加速器集成在一起，以实现科学应用所需的吞吐量。然而，在这样的系统中，需要相当大的努力来设计异构组件之间的有效通信机制。目前，HA与系统架构没有完全集成;将计算从CPU卸载到HA增加了大量的通信开销。该研究项目通过许多不同的技术探索解决这一问题的综合方案。该项目在研究出版物、研究生监督和少数民族教育方面具有广泛的影响，因为UCR是一个少数民族服务机构。该项目将通过静态编程和运行时优化开发新的CPU-GPU通信技术。它将开发一种可分负载理论（DLT）技术，将通信与计算重叠，并优化CPU和GPU之间的数据传输时间和大小。研究还将开发运行时技术，该技术可以监视执行的效率，并通过考虑不同应用程序的执行行为来动态地改变传输参数。架构变化将被纳入GPU中，以根据GPU内部的任务执行启动数据传输。将开发共享虚拟存储器（SVM）架构的设计，其中加速器和系统存储器共享单个虚拟地址空间;系统中的CPU和HA将通过SVM进行通信。硬件控制器，内存管理单元（MMU），GPU缓存架构，缓存一致性协议，以及GPU和CPU内核之间的其他接口也将被设计。该项目提出了合适的混合高速缓存一致性协议和高效的互连网络可扩展的系统设计。最后，将开发运行时系统和软件接口，可以在异构多核架构上执行多个多线程应用程序。

Future chip multiprocessors (CMPs) will have silicon space and technology to incorporate hundreds of cores. The trend is to integrate tens of cores and hardware accelerators (HAs), such as GPUs, on a single platform. The proposed heterogeneous architecture will enable future chips to operate within their power budgets while providing the high-throughput per Watt required for large scientific applications. Many of the top-500 supercomputers integrate thousands of CPUs with GPU accelerators to achieve the desired throughput for scientific applications. Considerable effort, however, is needed to design efficient communication mechanisms between heterogeneous components in such a system. Currently, HAs are not fully integrated with the system architecture; offloading computation from the CPU to the HAs adds large communication overhead. This research project explores comprehensive solutions to this problem through many different techniques. The project has significant broader impact in terms of research publications, graduate student supervision, and minority education because UCR is a minority serving institution.This project will develop new CPU-GPU communication techniques through static programming and run-time optimization. It will develop a divisible load theory (DLT) technique to overlap communication with computation, and optimize the time and size of data transfer between the CPU and GPU. The research will also develop run-time techniques that can monitor the efficiency of execution and dynamically change the transfer parameters by considering the execution behaviors of different applications. Architectural changes are to be incorporated in the GPU to initiate data transfers based on task execution inside the GPU. Design of the shared virtual memory (SVM) architecture is to be developed, where the accelerator and system memories share a single virtual address space; and CPUs and HAs in the system will communicate through the SVM. The hardware controllers, memory management unit (MMU), GPU cache memory architectures, cache coherence protocols, and other interfaces between the GPU and CPU cores will also be designed. The project proposes suitable hybrid cache coherence protocols and efficient interconnection networks for scalable system design. Finally, run-time system and software interfaces will be developed that can execute multiple multithreaded applications on a heterogeneous multicore architecture.