SaTC: STARSS: Design of Secure and Anti-Counterfeit Integrated Circuits

硬件安全，无论是用于攻击还是防御，都不同于软件、网络和数据安全，因为攻击者可能会找到物理篡改设备的方法，而不会留下任何痕迹，并误导用户相信硬件是可信的。此外，新的攻击模式、非法回收和难以检测的特洛伊木马程序的出现使硬件保护成为一项日益具有挑战性的任务。安全硬件集成电路的设计需要理想地基于多层保护的用于身份验证的新方法。这个项目开发了一种新的框架，将安全中的异构性和层次性和多层的混淆嵌入到集成电路的设计中。该项目采用基于服务器的全局身份验证和第三方供应商组件的本地身份验证相结合的方式，减少了与服务器的通信，从而减少了通信开销以及身份验证中的错误。研究人员探索了通过有意的电压压力和认证层次的权衡来增加基于SRAM的物理不可克隆函数(PUF)的健壮性的新方法。该项目研究基于有限状态机(FSM)状态转换图的修改的模糊技术，以及使用从测试芯片收集的数据开发和验证的模糊度量。

Hardware security, whether for attack or defense, differs from software, network, and data security in that attackers may find ways to physically tamper with devices without leaving a trace, and mislead the user to believe that the hardware is authentic and trustworthy. Furthermore, the advent of new attack modes, illegal recycling, and hard-to-detect Trojans make hardware protection an increasingly challenging task. Design of secure hardware integrated circuits requires novel approaches for authentication that are ideally based on multiple layers of protection. This project develops a novel framework for embedding heterogeneity and hierarchy in security and obfuscation at multiple layers into the design of integrated circuits. The project uses a combination of server-based global authentication combined with local authentication of components from third-party vendors reduces communication with the server, thus reducing the communication overhead as well as error in authentication. The investigators explore new approaches to increasing robustness of SRAM based physical unclonable functions (PUFs) by intentional voltage stress, and the tradeoffs in hierarchies of authentication. The project investigates techniques for obfuscation based on modifications of finite state machine (FSM) state transition graphs, and obfuscation metrics that are developed and validated using data collected from test chips.