SHF: Small: SlackTrack: Efficiently Exploiting Circuit Slack in Multi-Cycle Datapaths

微处理器和片上系统行业越来越关注移动平台，在移动平台上，最大限度地延长电池寿命是至关重要的。因此，静态和动态功耗现在是通用微处理器的主要设计限制。作为回应，芯片设计人员正在集成大量定制的片上加速器，这些加速器可以降低能耗，因为它们的控制逻辑、数据路径、互连和存储器是为特定任务量身定做的。该项目解决了加速器时钟存储元件中剩余功耗的主要来源，并研究了具有极少此类元件的新型加速器的设计。如果在设计高能效、高性能芯片方面没有这些戏剧性的创新，未来纳米技术的持续器件规模可能不再在实用或性能方面提供实质性回报。因此，微处理器行业，乃至整个计算机行业，在维持以增长为基础的商业模式方面面临着严峻的挑战，这种模式已经维持了40年。这项研究具有广泛的行业和经济影响，因为它有助于应对或避免这些挑战。这个项目的发现将被整合到研究生水平的课程中，这将帮助学生更深入地了解电力墙问题，这是建筑师在不久的将来面临的一大挑战。消除计时元件带来的管理费用将使加速器设计接近计算成本的真正能量下限。此外，流水线锁存器移除还暴露了改进数据路径电路的功率效率和性能的额外机会。最重要的是，由于多周期数据路径中的关键延迟路径跨越多个时钟周期，并且比基本朴素流水线遍历更多级别的逻辑，因此随机和芯片内变化将使关键路径减慢的可能性大大降低。换句话说，由于关键路径比基本情况下长两倍、四倍甚至更多，随机和芯片内工艺变化在较长的总延迟路径上被摊销，并且更有可能抵消彼此的影响，从而导致对可实现周期时间的较小净影响。可以利用这种收紧的差异来减少设计时裕度，从而允许数据路径在给定频率的较低电压下工作。此外，用于测量和控制电路运行中的可用松弛的新型运行时方法支持激进的时序推测，允许数据路径以接近标称的频率运行，同时将工作电压降至最低。

The microprocessor and system-on-chip industry is increasingly focused on mobile platforms, where maximizing battery life is paramount. As a result, static and dynamic power consumption are now primary design constraints for general-purpose microprocessors. In response, chip designers are integrating a plethora of customized on-die accelerators, which reduce energy consumption because their control logic, datapaths, interconnect, and memory are tailored for a specific task. This project tackles the main remaining source of power consumption in accelerators clocked storage elements and investigates the design of novel accelerators with very few such elements. Without these kinds of dramatic innovations in the design of power-efficient, high-performance chips, the continued device scaling of future nanometer technologies may no longer provide substantial returns in utility or performance. As a result, the microprocessor industry, and by extension, the computer industry as a whole, faces a serious challenge in maintaining the growth-based business model that has sustained it for four decades. This research has broad industry- and economy-wide impact since it helps to address or avert these challenges. The findings from this project will be integrated into graduate level courses which will help students get a more in depth understanding of the power wall issue which is a big challenge for architects in the near future.Removing the overheads imposed by clocked elements will enable accelerator designs to approach a true energy lower bound for the cost of computation. Furthermore, pipeline latch removal also exposes additional opportunities for improvement to the power efficiency and performance of datapath circuits. Most importantly, since the critical delay paths in a multi-cycle datapath span multiple clock cycles and traverse many more levels of logic than the base naive pipeline, the likelihood that random and within-die variations will slow down a critical path is substantially lower. In other words, since critical paths are two, four, or even more times longer than in the base case, random and within-die process variations are amortized over a longer total delay path and are more likely to cancel each others' effects, leading to a smaller net effect on achievable cycle time. This tightened variance can be exploited to reduce design-time margins, allowing the datapath to be operated at a lower voltage for a given frequency. Furthermore, novel run-time approaches for measuring and controlling available slack in the circuit's operation enable aggressive timing speculation, allowing the datapath to run at nearly nominal frequencies while minimizing operating voltage.