Heterogeneous Interconnect Stitching Technology (HIST) For High-Performance Computing Systems

现代生活的各个方面（例如，经济、健康和通信）依赖于先进的电子技术。因此，发现改善电子系统性能的方法将直接导致生活质量的改善。此外，提高电子产品的能源效率直接影响社会，因为它减少了现代数据中心的碳足迹，并延长了无处不在的移动的设备的寿命。本项目旨在通过探索基于异构互连拼接的新电子集成概念来提高电子系统的性能和能源效率。在所提出的集成方法的原则创新是在封装的表面上使用针脚芯片，以形成密集和低能量的组装芯片之间的互连。此外，组装的芯片使用多高度和多间距可压缩微互连件互连，所述微互连件是高密度机械柔性互连件，其实现所有芯片之间的鲁棒互连。为了实现我们的目标，以下基础研究课题进行了研究：1）在多芯片组件使用互连拼接电源噪声的分析; 2）实验演示的2x2阵列的芯片使用互连拼接组装;和3）提取频率依赖的寄生的可压缩微互连高达50 GHz。所有的研究将在格鲁吉亚技术，这是美国国家科学基金会支持的国家纳米技术协调基础设施计划的节点之一。这使我们能够轻松地让K-12学生接触这项研究，并鼓励他们追求科学和工程教育。拟议的研究还将涉及研究生和本科生进行研究与多个学科，包括电气工程，机械工程和化学工程。这些研究经验将提高他们的教育和更好地准备学生在工业中工作，因为他们已经有一个基本的了解如何不同的学科相互作用的电子系统。电子计算系统的性能和功耗越来越多地由互连决定。提出的异质互连拼接技术（HIST）可以大大减少组件之间的互连长度，从而提供更高的带宽密度，降低每比特的能量。此外，拟议的研究将使有源器件（光子，逻辑，存储器等）的集成成为可能。非常接近（即，面对面键合）;从而大大降低了电寄生效应并提高了互连密度。但是，由于组装封装的功率密度增加，所提出的集成方法可能加剧功率输送的挑战。因此，拟议研究的智力价值是双重的。首先，拟议的研究将发展的功率传输网络设计的基本理解，在拟议的异构集成方法，以尽量减少寄生引起的电压降和开关噪声作为几个技术参数的函数。其次，拟议的研究将通过实验证明关键的互连和组装技术，这些技术将实现低功耗和高性能的计算系统。实验工作将特别侧重于开发一个使用针脚芯片互连的2x2芯片阵列，以及高达50 GHz的HIST互连通道的特性。该实验研究还将探索多高度和多间距可压缩微互连的稳健和高产量批量规模制造及其机械可靠性。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Every aspect of modern life (e.g., economy, health, and communication) is dependent on advanced electronics. As such, discovering methods that improve the performance of electronic systems will directly lead to improvements in quality of life. Moreover, improving the energy efficiency of electronics directly impacts society as it reduces the carbon footprint of modern data centers and increases the lifetime of ubiquitous mobile devices. This project aims to improve both the performance and energy efficiency of electronic systems by exploring a new electronic integration concept based on heterogeneous interconnect stitching. The principle innovation in the proposed integration approach is the use of stitch chips on the surface of a package to form dense and low-energy interconnects between the assembled dice. The assembled chips, moreover, are interconnected using multi-height and multi-pitch compressible micro-interconnects, which are high density mechanically flexible interconnects that enable robust interconnection between all chips. To accomplish our objectives, the following fundamental research topics are investigated: 1) analysis of the power supply noise in multi-die assemblies using interconnect stitching; 2) experimentally demonstrating the assembly of a 2x2 array of chips using interconnect stitching; and 3) extracting the frequency-dependent parasitics of the compressible micro-interconnects up to 50 GHz. All research will be performed at Georgia Tech, which is one of the nodes within the NSF supported National Nanotechnology Coordinated Infrastructure program. This enables us to easily expose K-12 students to this research and encourage them to pursue science and engineering education. The proposed research will also involve the graduate and undergraduate students conducting the research with multiple disciplines that include electrical engineering, mechanical engineering, and chemical engineering. Such research experience will enhance their education and better prepares students to work in industry because they would already have a fundamental understanding of how different disciplines interact with each other in electronic systems.The performance and power dissipation of electronic computing systems have become increasingly dominated by interconnections. The proposed Heterogeneous Interconnect Stitching Technology (HIST) can greatly reduce interconnect length between components; thereby offering higher bandwidth density at reduced energy per bit. Moreover, the proposed research will enable the integration of active devices (photonic, logic, memory, etc.) in very close proximity (i.e., face-to-face bonding); thereby greatly reducing electrical parasitics and improving interconnect densities. But, the proposed integration approach may exacerbate the challenges in power delivery due to increased power density of the assembled package. As a result, the intellectual merit of the proposed research is twofold. First, the proposed research will develop fundamental understanding of the power delivery network design in the proposed heterogeneous integration approach to minimize parasitics-induced voltage drops and switching noise as a function of several technology parameters. Second, the proposed research will experimentally demonstrate the key interconnect and assembly technologies that will enable low-power and high-performance computing systems. The experimental effort will specifically focus on developing a 2x2 array of dice interconnected using stitch chips and the characterization of the HIST interconnect channels up to 50 GHz. The experimental research will also explore robust and high-yield batch-scale fabrication of multi-height and multi-pitch compressible micro-interconnects as well as their mechanical reliability.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.