Investigation of the long-term degradation of the high-frequency behavior of SiGe heterojunction bipolar transistors and circuits

硅-锗(SiGe)异质结双极晶体管(HBT)的最新技术发展使其最高工作频率达到500 GHz或更高，击穿电压(BVCEO)为1.6V，即使在工业原型工艺中也是如此。将高速HBT电路与中等成本的数字CMOS相结合而产生的BiCMOS技术，以及远至太赫兹区域的SiGe HBT性能预测，激发了人们对将毫米波和太赫兹频谱用于紧凑型商业电子应用的越来越大的兴趣。然而，如此高的性能是以非常高的电流密度、高自加热和低击穿电压为代价的，这些目前被认为限制了高频下的输出功率。然而，推动设备性能界限，上述影响可能会导致设备降级的加速。到目前为止，后者仅由静态安全工作区(SOA)描述，使用与高频电路设计几乎无关的静态基本电流，而有关高频(HF)操作下相关性能损失的信息尚未获得。在该项目的第一阶段，证明了SiGe HBT非常坚固耐用，在发生可测量的退化之前，可以远远超过铸造厂推荐的SOA值。这意味着有可能在高频下实现比目前假设的更大的输出功率。此外，对于测量的器件几何形状，已经发现了由于动态应力而导致各种与高频性能相关的参数退化的实验证据。因此，该项目第二阶段的主要目标是：(I)对先进的SiGe HBT的动态退化进行系统的实验评估，作为几何和频率的函数，以调查观察到的退化的物理根源。(2)探讨在电路设计过程中可实现的高频输出功率限制和与退化相关的权衡。(Iii)对观察到的退化效应进行紧凑建模，并开发一种估计高频电路模拟和设计过程中退化和可靠性的方法。(Iv)对选定的高频电路积木进行实验应力测试，并与电路模拟比较其性能随时间的退化。这项工作将跨越很宽的频率范围(10 GHz到180 GHz)，并将大大超出传统的静态可靠性测试。它的结果将使高频电路设计包括相关晶体管参数的退化效应。

Recent technology development of silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) has led to maximum operating frequencies of 500 GHz and beyond at 1.6 V breakdown voltage (BVCEO) even for industry prototyping processes. BiCMOS technology, resulting from combining high-speed HBT circuits with moderate-cost digital CMOS, and SiGe HBT performance projections far into the THz region, have spurred increasing interest in utilizing the millimeter (mm)-wave and THz frequency spectrum for compact commercial electronic applications. Such high performance comes though at the cost of very high current densities, high self-heating, and low breakdown voltages which are presently assumed to limit the output power at high frequencies. Pushing the device performance boundaries though, the above mentioned effects can lead to an acceleration of device degradation. So far, the latter is only described by a static safe operating area (SOA), using a static base current that is mostly irrelevant for HF circuit design, while information on the associated loss of performance under high-frequency (HF) operation has not been available. In the first phase of this project, it was demonstrated that SiGe HBTs are extremely rugged and can be operated far beyond the foundry recommended SOA before a measurable degradation occurs. This implies a potential for achieving at high frequencies significantly larger output power than presently assumed. Also, for the measured device geometry, experimental evidence has been found for degradation of various HF performance related parameters due to dynamic stress. Therefore, the main objectives of this second phase of the project are: (i) Systematic experimental evaluation of dynamic degradation in advanced SiGe HBTs as function of geometry and frequency for investigating the physical origin of the observed degradation. (ii) Exploration of the achievable high-frequency output power limit and associated degradation related trade-offs during circuit design. (iii) Compact modeling of the observed degradation effects and development of an approach for estimating degradation and reliability during HF circuit simulation and design. (iv) Experimental stress tests of selected HF circuit building blocks and comparison of their performance degradation over time with circuit simulation. This work will span over a wide frequency range (10 GHz to 180 GHz) and will go significantly beyond conventional static reliability tests. Its results will enable HF circuit design including degradation effects of the relevant transistor parameters.