Extreme broadband integrated photonic electronic receiver on silicon substrate

电子电路的带宽从根本上受到可用晶体管的渡越频率的限制。因此，光通信系统异常高的传输容量只能通过大量并行使用电子电路来开发。该项目第一阶段的基本思想是一个光子预处理电路，然后是一个特殊的时间交织电子解复用电路。SPP 2111第二阶段的目标是将概念扩展到完全可重构的超宽带双偏振光子接收器，并结合大规模并行化的电子电路和解复用模拟输出。与第一阶段的混合设置相反，现在计划采用单芯片单片集成。整个系统的带宽将通过不同的步骤得到改善：通过重新设计最先进的光栅耦合器来增加光输入带宽，以覆盖超过50 x 200 GHz的WDM信道。通过重新设计放大器和解调器级并应用极化多路复用来最大化数据吞吐量。接收器的预期可重新配置性通过基于低损耗多模干涉仪和通用马赫曾德干涉仪的光学非阻塞交换结构来实现。在第二阶段，所有的结构，包括偏振复用器，开关结构，光电二极管，放大器和模拟解复用器部分将单片集成在一个芯片上的EPIC技术的IHP。由于多路分解，输出端的电气带宽要求更加宽松，因此后续ADC可通过焊线连接。

The bandwidth of electronic circuits is fundamentally limited by the transit frequency of avail-able transistors. As a consequence, the exceptionally high transmission capacity of optical communication systems can only be exploited with massive parallel usage of electronic cir-cuits. The basic idea of the project’s first phase was a photonic preprocessing circuit followed by a special time interleaving electronic demultiplexing circuit. The aim of the second phase of the SPP2111 is the expansion of the concept to a fully reconfigurable ultra-broadband dual polarization photonic receiver in combination with a massive parallelization of electronic cir-cuits and demultiplexed analog outputs. In contrast to the hybrid setup of the first phase, now a single chip monolithic integration is projected. The bandwidth of the total system will be im-proved by different steps: The optical input bandwidth will be increased by redesigning the state-of-the-art grating couplers to cover more than 50 x 200 GHz WDM channels. Data throughput is maximised by redesigning of the amplifier- and demux-stages and applying po-larisation multiplex. The intended reconfigurability of the receiver is enabled by optical non blocking switch fabrics that are based on low-loss multi-mode interferometers and gener-alized Mach-Zehnder interferometers. In this second phase, all structures, including polariza-tion multiplex, switch fabric, photodiode, amplifiers and the analog demultiplexer parts will be monolithically integrated on a single chip in the EPIC technology of IHP. Due to the demulti-plexing, the electrical bandwidth requirements at the outputs are more relaxed, thus subse-quent ADCs can be connected via bond wires.