Research on Automatic Synthesis of Self-Checking Processors.

自检电路设计已被广泛认为是容错系统并发错误检测的关键技术。已经建立的重要概念包括：完全自检（TSC）电路，定义为故障安全（FS）和自检（ST），强故障安全（SFS）电路，代码分离（CD）电路，包括检查器作为一个特殊的类别，以及强代码分离（SCD）电路。SFS电路实现了TSC的目标，即产生一个非码字作为由于故障引起的第一个错误输出。SCD电路总是将非码字输入映射到非码字输出，即使在存在故障的情况下，只要故障是不可检测的。因此，由SFS功能电路组成的电路结构，其输出由SCD检查器监测，有效地提供了实现TSC目标的最大类别的自检电路。两个或多个功能电路可以相互连接以组成一个更大的逻辑网络。如果网络中嵌入的多个元件功能电路不仅是SFS，而且是SCD，则为了使整个逻辑网络实现TSC目标，不需要对元件电路的输入进行SCD检查。在本研究中，为实现有效实现TSC目标的大型逻辑网络，建立了两种重要的设计技术。首先，提出了一种系统的SFS和SCD顺序电路设计方法，大量使用高度结构化的逻辑阵列。其次，提出了一种组合电路和顺序电路的嵌入式逻辑函数的重映射技术，它们相互连接以组成更大的逻辑网络。所提出的技术允许在正常工作中充分行使每个组件功能电路的嵌入式输入接口，从而证明整个逻辑网络是SFS和SCD。在这些设计技术的基础上，实现了一个用于自检逻辑网络的自动合成器原型系统，并证明了它对自检处理器的自动合成是有用的。少

Self-checking circuit design has been widely recognized as an essential technique for concurrent error detection in fault-tolerant systems. Important concepts which have been well established include : totally selfchecking(TSC)circuits which are defined to be both fault-secure(FS)and self-testing(ST), strongly faultsecure(SFS)circuits, code-disjoint(CD)circuits which include checkers as a special class, and strongly codedisjoint(SCD)circuits. SFS circuits achieve the TSC goal of producing a non-codeword as the first erroneous output due to a fault. SCD circuits always map non-codeword inputs to non-codeword outputs even in the presence of faults so long as the faults remain undetectable. Thus, the circuit structure which consists of an SFS functional circuit with its output monitored by an SCD checker effectively provides the largest class of self-checking circuits that achieve the TSC goal. Two or more functional circuits may be interconnected to compose a larger logic network. If a c … More omponent functional circuit embedded in the network is not only SFS but also SCD, the input of the component circuit need not be monitored by an SCD checker in order for the entire logic network to achieve the TSC goal. In this research, two important design techniques have been established for the realization of a large logic network that effectively achieves the TSC goal. First, a systematic design method is presented for SFS and SCD sequential circuits with the intensive use of highly structured logic arrays. Second, a remapping technique is presented for embedded logic functions of both combinational and sequential circuits which are interconnected with each other to compose a larger logic network. The proposed technique allows the embedded input interface of each component functional circuits to be fully exercised in normal operation so that the entire logic network proves to be SFS and SCD. Based on these design techniques, a prototype system of an automatic synthesizer for self-checking logic networks has been implemented, and shown to be useful for the automatic synthesis of self-checking processors. Less