"Investigation of Cold Electronics Semiconductor LSI"

随着高速、高密度的要求，超大规模集成电路的集成密度逐年提高。值得注意的是，即使在目前，逻辑超大规模集成电路的集成密度也受到芯片热性能的限制，而逻辑超大规模集成电路需要高功耗才能实现高速运行。虽然基于约瑟夫森逻辑电路的低温电子技术是高速高密度的大规模集成电路之一，但我们注意到基于Si VLSI技术的低温电子技术是最有前途的候选人，它可以突破目前VLSI的局限性。本研究项目在以下主题下进行：1。开发一种新的封装概念，其热容量比传统封装大一到两个数量级。提出了一种新的低温工作高速硅MOSFET的设计原理，并制作了用于低温工作的基本MOS器件。在本课题中，我们用了四年（1987-1990）的时间对冷电子进行了详细的研究，取得了以下成果：我们提出了“微通道鳍封装”，利用AIN钝化层作为芯片内部的散热器，微通道鳍作为芯片的有效散热方法。利用二维/三维动态热分析模拟器对新封装的热性能进行了评估。当采用水冷微通道散热片时，VLSI芯片的耗散功率高达1.5kW/cm^2，是完全允许的。在1平方厘米的芯片上充分集成了每个栅极3mW的500k栅极ECL电路。压缩风冷微通道的允许耗散功率高达30W/cm^2。微通道翅片封装的热容量比传统封装大一到两个数量级。我们提出了一种与操作温度有关的新的标度理论——“温度标度理论”。利用二维/三维器件模拟器，我们发现电流-电压特性随工作温度成比例减小，而移动载波分布保持不变。根据温度标度理论，0.1mum MOSFET的最佳电源电压为1-1.5V，栅极延迟时间估计为1.6psec。此外，我们还制作了lab_6栅极MOSFET，用于低温下高速E/D MOSLSI的无冻出耗尽型MOSFET。通过LaB_6/SiO_2/p-Si MIS结构的C-V曲线确定LaB_6薄膜的功函数为3.5eV。采用自对准技术制备的lab_6栅极MOSFET具有FET的特性。少

The integration density of VLSI is increasing year by year with the requirement of high speed and high density. It should be noted that, even at present time, the integration density of logic-VLSI which requires the large power dissipation for high speed operation is limited by the thermal capability of the chip. Although cryoelectronics based on the Josephson logic circuit is one of the high-speed and high-density LSI's, We notice that cold electronics based on Si VLSI technology is the most promising candidate which can break through the present limitation of VLSI. This research project was carried out under the following subjects :1. To develop a new package concept in which the thermal capability is one or two order larger than that of the conventional packages.2. To develop a new design principle of low-temperature operated high-speed Si MOSFET, and to fabricate basic MOS devices for low-temperature operation. In this research project, we carried out detailed work on cold electron … More ics for four years (1987-1990) and obtained the following results :1. We proposed "a microchannel fin package" utilizing an AIN passivation layer as the heat spreader inside the chip and a microchannel fin as the efficient heat removal method from the chip. Thermal capability of the new package was evaluated using our simulator of dynamic thermal analysis in two/three dimensions. When the water-cooled microchannel fin is used, the dissipation power in a VLSI chip is quite allowable as high as 1.5kW/cm^2. More than 500k-gate ECL circuits with 3mW per gate are sufficiently integrated on a 1-cm^2 chip. When a compressive-air-cooled microchannel fined, the dissipation power is allowable as high as 30W/cm^2. The thermal capability of the microchannel fin package is one or two order larger than that of the conventional package.2. We proposed a new scaling theory, "a temperature-scaling theory", relating to the operation temperature. Using our device simulator in two/three dimensions, we found that current-voltage characteristics were scaled down in proportion to the operation temperature, while the mobile-carrier distribution was kept constant. According to the temperature scaling theory, the optimum supply voltage for 0.1mum MOSFET is 1-1.5V and the gate delay times is estimated to be 1.6psec. Furthermore, we fabricated a LaB_6-gate MOSFET for freeze-out-free depletion-type MOSFET of high-speed E/D MOSLSI at low temperature. The work function of LaB_6 thin film was determined to be 3.5eV from C-V curves of LaB_6/SiO_2/p-Si MIS structure. The LaB_6-gate MOSFET fabricated using the self-align technique exhibited FET characteristics. Less