Single Electron Integrated Circuits Based on A BDD Architecture Utilizing Quantum Dots Controlled by Nano-Schottky Gates

本研究的目的是探讨一种新颖的单电子积体电路的基础上二进制决策图（BDD）架构利用量子点控制的纳米肖特基闸。（1）提出了一种新的“六边形BDD量子电路方法”，将BDD结构实现在高密度的六边形纳米线网络上。各种逻辑子系统和算术逻辑单元（ALU）的成功设计利用新的电路方法。（2）利用肖特基栅控制的GaAs基刻蚀纳米线实现了单元BDD器件（节点器件）。它们从低温到室温都表现出明显的路径切换特性。WPG控制的单电子节点器件的功率延迟积（PDP）小到10 μ <-22>J。通过直接测量截止频率，实验证实了WPG开关的GHz工作能力。（3）B ...更多信息 在WPG控制的刻蚀六边形纳米线网络上制作了双BDD逻辑电路，它们在低温下正确地工作在量子机制中。他们被发现是可能的正确操作，即使在室温下，通过权衡PDP值。然后，实现4500万个器件/cm ^2的高密度集成电路制造工艺已经建立。利用该工艺制作了2位BDD加法器电路，并验证了其正确运算，同时成功制作了8位加法器。（4）研究了在图案化衬底上通过分子束外延选择性生长形成六角量子纳米线网络结构，建立了GaAs基2.4亿节点/cm ^2和InP基1giga节点/cm ^2的超高密度网络制备技术。利用选择性分子束外延生长的纳米线成功地制作了分支开关和节点器件，并证实了它们的正确操作。（5）针对III-V族半导体量子纳米结构的表面钝化问题，研究并优化了超薄Si和c-GaN界面控制层（ICLs）表面钝化技术。结果表明，通过制备富Ga（4×6）重构表面作为ICL形成的初始表面，成功地钝化了GaAs表面。在SiO_2/GaAs界面上获得了4×10^ cm^ eV^的极小界面态密度<10><-2><-1>。少

The purpose of this research was to investigate a novel single electron integrated circuit based on a binary-decision diagram (BDD) architecture utilizing quantum dots controlled by nano-Schottky gates. Main results are listed below :(1)A novel "hexagonal BDD quantum circuit approach" for realization of quantum LSIs, in which the BDD architecture is implemented on hexagonal nanowire network in high dense, was proposed. Various logic subsystems and arithmetic logic units (ALUs) were successfully designed utilizing the novel circuit approach.(2)Elemental BDD devices (node devices) were realized using GaAs-based etched nanowires controlled by Schottky wrap gates (WPGs). They showed clear path switching characteristics from low temperature to room temperature. Power-delay product (PDP) of WPG-controlled single electron node devices was found to be as small as 10^<-22> J. Capability of GHz operation of WPG switches was confirmed experimentally by direct measurement of cut-off frequency.(3)B … More asic BDD logic circuits were fabricated on etched hexagonal nanowire networks controlled by WPGs and they operated correctly in a quantum regime at low temperature. They were found to be possible to operate correctly even at room temperature by trading off of PDP values. Then, high-density integrated circuit fabrication process realizing 45 million devices/cm^2 has been established. Utilizing this process, 2-bit BDD adder circuits were fabricated and their correct operations were confirmed, and 8-bit adder was also successfully fabricated.(4)Formation of hexagonal quantum nanowire network structures by MBE selective growth on patterned substrates was investigated and ultra-high density network fabrication technology of 240 million nodes/cm^2 for GaAs-based systems and 1 giga nodes/cm^2 for InP-based systems have been established. Branch switches and node devices were successfully fabricated utilizing the selectively MBE grown nanowires and their correct operations were confirmed.(5)For surface passivation of III-V semiconductor quantum nanostructures, a technique using ultra-thin Si and c-GaN interface control layers (ICLs) was investigated for III-V materials and optimized. It was found that GaAs surfaces was successfully passivated by preparation of Ga-rich (4×6) reconstructed surface as an initial surface for the ICL formation. Ultra-small minimum interface state density of 4×10^<10> cm^<-2>eV^<-1> was obtained in the SiO_2/GaAs interface. Less