LSI Test Technology for Evaluating Soft-Error-Rates in Combinational Logic Circuits

当暴露在辐射环境中时，超大规模积分(VLSI)表现出被称为“软误差”的瞬时误差。由于晶体管的激进小型化，软错误现在正成为像CPU这样的逻辑VLSI的严重故障源。因此，需要在辐照测试中对所制造的逻辑芯片的软错误率进行实验评估。为此，我们在本研究项目中开发了一种新的LSI测试技术。为了准确评估逻辑芯片的软错误率，应满足以下两个要求。逻辑VLSI由组合逻辑电路组成的复杂网络组成，这些电路由反相器等逻辑门和触发器等时序元件组成。需要对散布在芯片中的每个顺序元件处的存储数据的辐射引起的颠倒的数目进行计数。此外，数据扰乱不仅由对顺序元件的直接辐射命中，而且还由锁存由对组合逻辑电路的辐射命中产生的名为“单事件瞬变，集合”的脉冲型噪声引起。前者通常被称为“时序元件中的软错误”，后者则被称为“组合逻辑电路中的软错误”。现在重要的是评估软错误对组合逻辑电路的影响。这两种软错误应该分别评估。我们的测试技术是基于扫描测试技术，该技术广泛应用于当今逻辑芯片的操作测试，因为它使我们能够直接写入和读取每个时序元素。我们开发了一种扫描触发电路和一种用于评估软错误率的辐照测试方法。我们已经通过实验证明了这项技术的有效性。此外，我们还成功地揭示了SOI-CMOS逻辑门中SET的详细脉宽分布，并发展了一种快速、准确的SET波形估计技术。

Very large scale integrations, VLSIs, exhibit transient errors called "soft errors" when exposed to radiation environments. As a result of aggressive miniaturization of transistors, the soft error is now becoming a serious failure source of logic VLSIs like CPUs. It is thus desired to evaluate experimentally soft-error rates of fabricated logic chips in irradiation tests. For the purpose, we have developed a new LSI test technology in this research project.To evaluate soft-error rates of logic chips precisely, the following two requirements should he satisfied. Logic VLSIs consist of complicated networks of combinational logic circuits built with logic gates like inverters and sequential elements like flip-flops. It is required to count up the number of radiation-induced upsets of stored data at each sequential element scattered in the chips. Moreover, the data upsets are induced by not only direct radiation hits to the sequential elements and also latching pulse-type noises named "single-event transients, SETs, " which are generated by radiation hits to combinational logic circuits. The former is generally called "soft errors in sequential elements, " and the latter "soft errors in combinational logic circuits." It is now important to evaluate the impact of the soft errors in combinational logic circuits in particular. These both types of soft errors should be evaluated separately.Our test technology is based on the scan test technology, which is widely used in today's logic chips for testing their operations because it enables us to write and read each sequential element directly. We have developed a scan flip- flop circuit and an irradiation test method for the soft-error rates evaluation. We have experimentally demonstrated the validity of the technology. Moreover, we have successfully revealed detailed pulse-width distributions of SETs in SOI-CMOS logic gates, and developed a fast and accurate estimation technique of SET waveforms.