Research on Advanced VLSI Test for Avoiding Signal Degradation

本研究解决了大规模集成电路高速扫描测试中的误测问题。首先，确定了测试向量在长敏化路径附近（关键区域）的过度开关活动是导致误测的主要原因。其次，通过考虑长敏化路径的敏化状态、接近信息和过渡水平，提出了一种识别风险测试向量的精确度量。此外，本研究提出了一种从测试集中提取影响关键区域切换活动的冗余位的方法，并设计了一种x填充方法来确定冗余位的逻辑值，从而有效地降低了关键区域的切换活动。在此基础上，建立了一种先进的防误测方案。

This research addressed the false test issues in at-speed scan testing of LSI circuits. First, it identified the excessive switching activity in the proximity (critical area) around a long sensitized path by a test vector as the main cause of false test. Next, it proposed an accurate metric for identifying risky test vectors by taking the sensitization status of long sensitized paths, proximity information, and transition level into consideration. Furthermore, this research proposed a method for extracting redundant bits from a test set that can impact the switching activity in critical areas and devised an X-filling method for determining logic values for the redundant bits so that switching activity in critical areas is effectively reduced. As a result, an advanced false-test-avoiding scheme has been established.