Modelling of Carrier Transport in Ultra Thin Body Transistors

国际半导体技术路线图要求积极扩展传统金属氧化物半导体场效应晶体管，因为传统器件将达到超过45纳米技术节点的极限。为了维持设备性能的预期增长，必须将新颖的超薄体晶体管引入生产。此外，硅器件主体和二氧化硅介质都必须被更高迁移率的半导体和更高的介电常数材料所取代。拟议的联谊会研究旨在开发一种能够准确模拟超薄体晶体管低维特性的最先进的蒙特卡罗器件模拟器。该模拟器将被用于优化超薄体结构，对未来的高迁移率材料进行基准测试，并研究高K电介质对沟道迁移率的影响。它还将重点开发渠道中不同的材料晶体取向。随附的研究拨款提案旨在建立一个新的蒙特卡罗模拟工具，并增强合作者在研究纳米线晶体管时使用的非平衡格林函数模拟器。

Aggressive scaling of the conventional metal-oxide-semiconductor field effect transistors is required by the International Technology Roadmap for Semiconductors as conventional devices will hit a limit beyond the 45 nm technology node. Novel, ultra-thin body transistors must be introduced into production in order to sustain the expected increase in device performance. Moreover, both the Silicon device body and the SiO2 dielectric have to be replaced with a higher mobility semiconductor and higher dielectric constant materials.The proposed fellowship research aims to develop a 'state-of-art' Monte Carlo device simulator which is capable of accurately modelling the low-dimensional properties of ultra-thin body transistors. The simulator will be employed to optimise the ultra-thin body architecture, to benchmark the prospective high mobility materials, and to investigate the impact of high-K dielectrics on channel mobility. It will also focus on the exploitation of different material crystal orientations in the channel. The accompanying research grant proposal aims to establish a new Monte Carlo simulation tool and enhancing the collaborators' Non-Equilibrium Green Functions simulator employed in the investigation of nanowire transistors.