Renaissance Germanium

在电子革命诞生之时，锗作为一种半导体材料正在经历复兴--甚至可能与硅相媲美。随着硅的热潮，锗吸引了人们的巨大兴趣。大胆地，但被许多人认为，它是一个潜在的候选者，可以在设想的硅开发结束(大约2020年)之后保持类似硅的技术和相关设备，并将该技术带入令人兴奋的新领域和性能制度。这项提议旨在探索以前没有研究过的GE的基本电子结构的一些有趣的方面和结果。有很好的理论论证表明，如果载流子沿着非传统的晶体方向移动，并且当Ge处于应变状态时，一些关键的性能参数可以显著提高。我们将研究这些新环境如何影响载流子(电子和空穴)的速度/迁移率和有效质量，以及阻碍它们运动(散射)的过程。该项目将由三个英国大学小组进行，这些大学小组专门从事这项研究，并以应变Ge的外延生长(Warwick)、纳米级结构表征的透射电子显微镜(TEM)(谢菲尔德)和载流子传输模型(Glasgow)而享誉国际。华威的工业标准CVD生长系统使我们处于独特的地位，可以为这一研究领域做出贡献，高质量的GE结构在该计划的早期就有很好的前景。欧洲领先的纳米加工实验室IMEC的参与，将使我们能够无与伦比地获得英国没有的工具。我们的知识产权将受到充分保护，并可被英国的许多公司利用。主要目标是研究这些基本上未尝试过的方向上的2D载体传输，并寻找与传统(100)方向相比，载体移动性方面的显著增强。类似的调查目前正在硅领域进行，现在正是在通用电气探索这一点的时候。考虑到IMEC在主要使用硅加工技术制造GE器件方面的最新进展，这项计划尤其及时。该计划由三个集成工作包组成：WP1-应变Ge沟道结构的生长和加工：将开发外延工艺，执行结构表征，包括高分辨率TEM，以及用于电测量的简单结构加工。WP2-调制掺杂掩埋沟道结构：初始评估和筛选取向和应变对空穴和电子传输的影响，快速瞄准优化的结构，特别是避免任何可能对电子传输不利的加工扰动效应。格拉斯哥器件建模小组将使用测量结果来开发/改进该材料系统的基本散射和迁移率模型，并为最终选择结构提供指导。WP3-表面沟道器件结构：包含栅电极以调制载流子数量并使其成为有源器件的结构。栅极与沟道之间由一层非常薄的新型(高k)介电材料隔开，这也将散射载流子。低至极低温度下的传输测量将使我们能够评估Ge提供的全部器件潜力。到项目结束时，我们有望在Ge表面取向、沟道方向和应变的全矩阵中彻底理解2D载流子传输的实际和理论方面。然后，这些知识可以被用来帮助实现纳米电子学和未来自旋电子学时代所需的新一代高性能设备。

Germanium, in at the birth of the electronics revolution, is experiencing a renaissance as a semiconductor material - possibly even rivalling silicon, and is attracting huge interest as the silicon end-game hots up. It is perceived, audaciously but by many, as a potential candidate to maintain silicon-like technology and associated devices well beyond the envisaged end of silicon development (around 2020) and also take the technology into exciting new areas and performance regimes. This proposal sets out to explore some of the intriguing aspects and consequences of the fundamental electronic structure of Ge not previously examined. There are good theoretical arguments to suggest that some critical performance parameters can be dramatically enhanced if carriers travel in non-conventional crystallographic directions and when the germanium is under strain. We will investigate how these new environments affect the velocity/mobility and effective mass of the carriers (electrons and holes) and the processes that impede their motion (scattering).The project will be conducted by three UK university groups uniquely positioned to undertake this research and with international reputations for epitaxial growth of strained Ge (Warwick), transmission electron microscopy (TEM) for structural characterization on the nanoscale (Sheffield) and carrier transport modelling (Glasgow). The industrial standard CVD growth system at Warwick puts us in a unique position to contribute to this field of research, with good prospects of the high quality Ge structures being available early in the programme. Participation of IMEC, the leading European nano-processing laboratory, will give us unparalleled access to tools not available in the UK. Our intellectual property will be fully protected and could be exploited by numerous companies in the UK.The principal objective is to study 2D carrier transport in these largely untried orientations and to look for significant enhancements in carrier mobility compared to the conventional (100) orientation. Similar investigations are currently underway in silicon and it is opportune to now explore this in Ge. It is particularly timely in the light of IMEC's recent progress in Ge device fabrication using essentially silicon processing techniques.The programme consists of three integrated workpackages:WP1 - Growth and processing of strained Ge channel structures: Epitaxial processes will be developed, structural characterisation performed including high resolution TEM, and simple structures processed for electrical measurement.WP2 - Modulation doped buried channel structures: Initial assessment and screening of orientation and strain influences on hole and electron transport, quickly targeting optimised structures and specifically avoiding any perturbing effects of processing that may be detrimental to electron transport. Results from the measurements will be used by the Glasgow Device Modelling Group to develop/refine basic scattering and mobility models for this materials system and provide pointers to final choice of structures.WP3 - Surface-channel device structures: Structures containing a gate electrode to modulate the carrier population and make it an active device. The gate is separated from the channel by a very thin layer of a new (high-k) dielectric material, which will also scatter the carriers. Transport measurements down to very low temperatures will allow us to appraise the full device potential offered by Ge.By the end of the project we would expect to have a thorough understanding of the practical and theoretical aspects of 2D carrier transport in the full matrix of Ge surface orientations, channel directions and strain. Such knowledge can then be used to great advantage in helping realise new generations of highly performing devices that are needed in the nanoelectronics and the futuristic spintronics era.