Enabling multicore chips: Bridging the programmability gap in today's parallel systems

过去两年见证了包含多个处理器的芯片的引入，这些芯片通常被称为多核芯片。这些芯片代表了计算机工业在可预见的未来提高计算机系统性能的手段：增加芯片中处理器的数量，而不一定改善单个处理器的性能。预计多核芯片中的处理器数量将在每一代硅芯片中翻一番，在十年多一点的时间内达到100个处理器。多核芯片具有巨大的性能改进潜力。遗憾的是，这种潜力可能不会轻易传递给普通消费者。这是因为今天的绝大多数软件都是为在单处理器上执行而编写的。习惯于看到他们的程序在更新的计算机上执行得更快的消费者，在这些程序被(重新)编写以在多个处理器上高效执行之前，不会再看到这样的改进。这种(重新)为多核编写程序的过程称为并行编程，对于软件开发人员和程序员来说，这一过程本身就很困难，导致了可编程性差距。事实上，多核制造商和软件开发商/程序员认为，这种可编程性差距是开发多核性能潜力的主要障碍。我们的研究目标是解决多核芯片的可编程性差距。我们将通过在编译器、运行时支持和处理器体系结构方面的创新来做到这一点，这些创新将(1)促进将现有的顺序软件移植到具有多核芯片的系统上的任务；(2)使编写并行程序的任务更容易和更高效；以及(3)更快地执行并行程序，无论是手动编写的还是由工具生成的。这些创新将使软件开发人员更容易为多核编写高效的程序，从而将其性能潜力传递给最终用户。

The last two years have witnessed the introduction of chips that contain more than one processor, commonlyknown as multicore chips. These chips represent the means by which the computer industry will to improve theperformance of computer systems in the foreseeable future: increase the number of processors in a chip withoutnecessarily improving the performance of the single processor. It is expected the number of processors in amulticore chip will double every silicon generation, reaching 100s of processors in a little over a decade.Multicore chips offer tremendous performance improvement potential. Regrettably, this potential may not beeasily delivered to the average consumer. This is because the vast majority of today's software is written toexecute on a single processor. Consumers, accustomed to seeing their programs execute faster on newercomputers, will no longer see such improvements until these programs are (re-)written to execute efficiently onmultiple processors. This process of (re-)writing programs for multicores, referred to as parallel programming,is inherently difficult for software developers and programmers, resulting in a programmability gap. Indeed,multicore manufacturers and software developers/programmers identified this programmability gap as the mainhurdle in exploiting the performance potential of multicores.The goal of our research is to address the programmability gap in multicore chips. We will do so throughinnovations in compilers, run-time support and processor architectures that will (1) facilitate the tasks ofporting existing sequential software to systems with multicore chips; (2) make the tasks of writing parallelprogramming easier and more efficient; and (3) execute parallel programs, whether manually written orgenerated by tools, faster. These innovations will make it easier for software developers to write efficientprograms for multicores and thus deliver their performance potential to end users.