Digital and Memory Circuits in nano-scale CMOS Technologies

以最先进的技术实现健壮的集成电路正变得越来越困难。工艺的规模化使得晶体管容易受到工艺变化的影响，单个晶体管的不正确运行可能会导致包含数百万个晶体管的芯片故障。通常使用尽可能小的晶体管尺寸来降低功率、能源消耗，并增加封装密度。不幸的是，尺寸越小的晶体管对工艺变化的敏感度越高。特别是，由于晶体管尺寸最小，低电压、低功率静态随机存取存储器(SRAM)电路表现出更高程度的变化。在这项研究中，我们将研究在功率和电压受限的环境中，数字SRAM电路的可变性感知设计。在微处理器中，多达70%-80%的晶体管位于SRAM中。因此，片上系统(SoC)的各个方面--功率、能量、产量、质量和可靠性都会受到SRAM的影响。

Realization of robust integrated circuits in state of the art technologies is becoming increasingly difficult. The technology scaling makes transistors susceptible to process variations, and improper functioning of a single transistor may lead to the chip failure containing several million transistors. Often small as possible transistor sizes are used to reduce power, energy consumption, and to increase the packing density. Unfortunately, transistors with smaller dimensions exhibit a higher susceptibility to process variation. In particular, low-voltage, low-power Static Random Access Memory (SRAM) circuits show higher degree of variation owing to smallest possible transistor dimensions. In this research, we will investigate variability-aware design of digital, SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) - power, energy, yield, quality, and reliability are influenced by SRAMs.