Digital and Memory Circuits in nano-scale CMOS Technologies

在目前的技术水平下，实现鲁棒集成电路变得越来越困难。技术尺度使得晶体管易受工艺变化的影响，单个晶体管的功能不正常可能导致包含数百万晶体管的芯片失效。通常使用尽可能小的晶体管尺寸来降低功率、能耗和增加封装密度。不幸的是，尺寸较小的晶体管对工艺变化的敏感性更高。特别是，低电压，低功耗静态随机存取存储器（SRAM）电路由于尽可能小的晶体管尺寸而表现出更高程度的变化。在本研究中，我们将研究功率和电压受限环境下数字SRAM电路的可变感知设计。在微处理器中，高达70-80%的晶体管都在ram中。因此，片上系统（SoC）的各个方面——功率、能量、产量、质量和可靠性都受到sram的影响。

Realization of robust integrated circuits in state of the art technologies is becoming increasingly difficult. The technology scaling makes transistors susceptible to process variations, and improper functioning of a single transistor may lead to the chip failure containing several million transistors. Often small as possible transistor sizes are used to reduce power, energy consumption, and to increase the packing density. Unfortunately, transistors with smaller dimensions exhibit a higher susceptibility to process variation. In particular, low-voltage, low-power Static Random Access Memory (SRAM) circuits show higher degree of variation owing to smallest possible transistor dimensions. In this research, we will investigate variability-aware design of digital, SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) - power, energy, yield, quality, and reliability are influenced by SRAMs.