Study single event effects in logic circuits with 28nm CMOS bulk and SOI technologies

在过去的四十年中，硅技术缩放通过增加晶体管密度和工作频率，同时降低每个晶体管的成本和能耗，显著改善了集成电路（IC）。然而，硅技术的规模化使得IC更容易受到高能粒子引起的单粒子效应（SEE）的影响。在一个设计良好的集成电路，软错误引起的SEE似乎是最麻烦的地面和高海拔或空间环境。存储单元是数字系统中软错误的主要来源之一，不同厂商的设计软错误率相差3个数量级。绝缘体上硅（SOI）工艺已成为一种有前途的技术，以减少电子系统中的软错误率。拟议项目的目标是开发采用最先进CMOS技术制造的容错逻辑电路，以降低思科交换机和其他电子产品的软错误率。 我们将研究先进的体和SOI CMOS技术（28纳米工艺）的SEE，并旨在开发容错数字存储和传感电路。各种技术，包括布局和设计技术将被用来开发容错存储单元。设备和原理图模拟工具将用于调查，以便有效地开发SEE缓解方法。制作的测试芯片将用脉冲激光、重离子、质子和中子束进行测试，以验证设计的有效性。来自不同测试设施的结果也将相互关联。一个PDF两个博士学生和一个导师的学生将接受培训，以促进技术的发展，并与工业伙伴密切合作。研究成果将产生可申请专利的技术，并在相关期刊和会议上发表。加拿大行业合作伙伴（思科加拿大）可以采用该项目开发的技术，以提高其产品（如交换机和线路卡）的可靠性。该项目还将提高萨斯喀彻温大学微电子可靠性研究小组的能力和专门知识。

Over the last four decades, silicon technology scaling has remarkably improved the integrated circuits (ICs) by increasing the transistor density and operating frequency while reducing the cost and energy consumption per transistor. However, the scaling of silicon technologies makes ICs more vulnerable to single event effects (SEEs) induced by energetic particles. In a well-designed IC, soft errors induced by SEEs appear to be the most troublesome both in terrestrial and high altitude or space environment. Storage cells are one of the major sources of soft errors in digital systems, and the soft error rates can be in 3 order differences for the designs from different vendors. Silicon-on-insulator (SOI) process has emerging to be a promising technology for reducing soft error rates in electronic systems. The objectives of the proposed project are to develop fault-tolerant logic circuits that are fabricated with the most advanced CMOS technologies in order to reduce the soft error rate in Cisco's switches and other electronic products. We will study SEE in both advanced bulk and SOI CMOS technologies (28nm process) and aim to develop fault-tolerant digital storage and sensing circuits. Various techniques including both layout and design techniques will be used to develop the fault-tolerant storage cells. Device and schematic simulation tools will be used for the investigation, so that SEE mitigation methods can be effectively developed. The fabricated test chips will be tested with pulsed laser, heavy ion, proton and neutron beams to verify the effectiveness of the designs. The results from different testing facilities will also be correlated. One PDF, two Ph.D. students and one mater's student will be trained to advance the technology and to work closely with the industrial partners. The research results will result in patentable technologies and publications in related journals and conferences. The Canadian industry partner (Cisco Canada) can adopt the technologies developed from this project to improve the reliability of their products such as switches and linecards. The project will also enhance the capability and expertise of the research group in the area of microelectronics reliability at the University of Saskatchewan.