Performance Optimization of VLSI Interconnect

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Interconnect is rapidly becoming one of the most important factors in influencing the behavior of integrated circuits. This project addresses the problem of developing next- generation computer-aided design tools to handle these problems. The objective of this work is to apply recent advances in fast simulation of interconnect to solve optimization problems in interconnect design. Specifically, problems related to the design of supply busses, clock networks and signal nets are being investigated. In case of supply nets, structured mesh topologies that provide a good tradeoff between performance and ease of analysis are being considered. In case of signal nets, the problem of building optimal rectilinear Seiner trees under an environment of resistive, capacitive and inductive effects are being studied, with consideration to the interactions with detailed routing. In addition to delay, the work incorporates considerations of signal integrity and manufacturability during the optimization.