CAREER: Gate-Level Performance Optimization of Pipelines and General Sequential Circuits

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This project is concerned with performance optimization of high- speed synchronous digital circuits It addresses the application of timing optimizations to pipelines and general sequential circuits in high-performance systems. The core of the research effort is directed towards the method of retiming at the gate level. Retiming is a sequential logic optimization technique that repositions memory elements, namely, edge-triggered flip-flops and level-triggered latches, within a circuits to optimize the timing behavior of the circuit. The use of retiming optimization methods, chiefly device sizing, is also being investigated. Under the educational part of this project, the PI is incorporating CAD techniques in the undergraduate program from the sophomore level by the use of CAD tools in teaching. At the graduate level, he is involved in developing courses, the supporting existing courses, and in advising graduate students. He is also exposing undergraduates to his research for a better appreciation of the state of the art, and to motivate them towards higher education. he is also contributing towards outreach activities by focusing towards distance education through teaching courses to sites in the state of Iowa via television, and around the country through the medium of satellite.