Mixed Signal Electronic Technologies: Joint Initiative Between NSF and SRC : Three-Dimensional Impedance Engineering of Substrates for Mixed Signal Integrated Circuit Applications

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0120368XieTechnological demand exists for mixed-signal integrated circuits based on Si VLSI. Such technology will enable the reduction of the form factor, power consumption, and circuit design complexity of mixed-signal IC's that are the core of portable electronics, personal communicators, the read-write channels of computer hard drives, and modems for internet access. The advancement of the technology is currently hampered by the cross-talk issue, for which there is no viable solution insight.The PIs propose an innovative solution to the problem. Through-the-wafer porous Si regions analogous to a moat are inserted between the noise producing and noise sensitive circuits to isolate electromagnetic interference (EMI). Such isolation is achieved via the high impedance nature of the porous Si region comparing to the alternative pathway of Si substrate for the EMI to reach true ground. The same porous Si regions can also be used to isolate high performance passive components (inductors and capacitors) from the substrate. Similar porous Si moat can be converted to highly conductive regions by coating the internal pore surfaces with metal. Highly conductive regions can serve as grounded shields for RF interference. Alternatively, through-the-wafer porous Si "posts" can be fabricated with porous Si removed afterward. This will result in deep vias. Metal can be introduced into the vias, resulting in Faraday cage type of structures for shielding electromagnetic interference. An appropriate name for the proposed research is three-dimensional impedance engineering of the substrate.In the proposed research, The PIs will scrutinize the effectiveness of all three approaches for RF cross-talk isolation. They will focus on the frequency range from 100 MHz up to above 40 GHz. This is the targeted frequency range by Si-based mixed-signal integrated circuits for the near future. By introducing this porous Si-based comprehensive process module into Si VLSI process flow, they will provide a unique solution to several of the most challenging issues present today in the Si mixed-signal IC technology.Their research will address the following critical issues relevant to the realization of the innovation. The issues include the isolation effectiveness, long-term stability of the isolation region, the preferred masking scheme and material, the method for introducing metal into the porous Si region, the mechanical integrity of the porous Si with and without metal coatings, the compatibility with Si VLSI processing, and potential contamination concerns.The proposed research encompasses materials science and electrical engineering. It will migrate from mostly material and processing issues at the beginning of the project, to RF circuit fabrication and testing towards the end of the project. The research will be carried out in collaboration with Conexant where their test chips will be fabricated, and Agere Systems (supporting our research in porous Si via SRC) where their initial study into this strategically important field started.In addition to the expected technological impact, the proposed research will serve the important function of educating a new generation of engineers by exposing them to the frontier of the information technology. Conducting thesis research on such a project will give them an education in the combined areas of fundamental materials science and a keen sense of the requirement of practical devices through the collaboration with industry. They will become members of the innovative workforce that has been the drive force for the prosperity of our society.