SHF:Small: Collaborative Research: Exploring 3-Dimensional Integration Strategies of STTRAM

SHF:Small：协作研究：探索 STTRAM 的 3 维集成策略

• 批准号: 1718474
• 负责人: Swaroop Ghosh
• 金额: $ 22.5万
• 依托单位: Pennsylvania State Univ University Park
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-08-01 至 2022-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1718474&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Exploring

The development of high-density memory is fueled by recent advancements in several critical areas ranging from big data analytics, Internet-of-Things (IoT), wearable electronics, smart phones, assistive devices, cybersecurity to weather tracking systems. Currently available conventional memory technologies face serious challenges in addressing these needs due to increased energy consumption, scalability limitations, and limited bandwidth. The objective of this proposal is to develop novel memory devices by enabling 3D integration of spin-torque transfer RAM devices (STTRAM) with appropriate selector diodes (SD). These type of memory devices will be massively scalable, energy-efficient, and fast which will open tremendous opportunities to integrate them in existing memory architectures to enable various futuristic applications. The project will integrate education by incorporating research outcomes in PI's academic courses. Industrial feedback will be sought via collaborations. Under-represented groups will be involved in science and engineering through several outreach programs at Penn State University (PSU) and University of Cincinnati (UC) such as Summer Research Opportunities Program (SROP) at PSU, and Emerging Ethnic Engineers (E3) program at UC which provides opportunities to the high-school students from the inner-city schools with economically challenged background to participate in internships and lab-experience activities. Undergraduate students will be involved in research via Research Experiences for Undergraduates (REU) program at both the universities. Dissemination of results will be accomplished by publications in high-impact scientific journals, conference presentations, and YouTube lecture videos. The intellectual merit of the project is in understanding the integration compatibility of STTRAM devices with SD and developing highly scalable 3D crossbar arrays of memory technologies based on integrated STTRAM and SD. The objectives will be achieved by executing the following specific aims: (i) modeling and simulation of STTRAM-SD arrays, (ii) resilience analysis and optimization studies to minimize the impact of device-level variabilities on performance metrics, (iii) optimization of STTRAM-SD architectures for high-performance computing and IoT, (iv) designing, fabrication, testing, and modeling of novel SD devices based on energy band-engineered and doping-engineered transition metal oxide and electrode stacks, (v) designing and fabrication of small-size STTRAM-SD arrays, electrical testing and modeling to benchmark simulations and experimental results. It is anticipated that the successful completion of this project will lead to a fundamental understanding of the compatibility of STTRAM with SD and provide a platform-technology to develop high-density memories which will have transformative impact on commercializing and advancing the futuristic applications.

在几个关键领域的最新进步范围从大数据分析，图像互联网（IoT），可穿戴电子设备，智能手机，辅助设备，网络安全到天气跟踪系统的最新进展，到达高密度记忆的发展。目前可用的常规记忆技术在满足能源消耗，可伸缩性限制和有限的带宽时面临严重的挑战。该建议的目的是通过使用适当的选择二极管（SD）启用3D整合的3D整合来开发新的记忆设备。这些类型的内存设备将非常可扩展，节能且快速，这将为将它们集成到现有内存体系结构中以启用各种未来派应用程序。该项目将通过将研究成果纳入PI的学术课程来整合教育。将通过合作寻求工业反馈。代表性不足的小组将通过宾夕法尼亚州立大学（PSU）和辛辛那提大学（UC）（PSU的夏季研究机会计划（SROP））以及在UC的UC计划中参与科学和工程学，从而为具有经济挑战性的背景的高级学院提供了机会，并在UC中提供了经济挑战性的实习生，并从事实习机会。本科生将通过两所大学的本科生（REU）计划的研究经验参与研究。结果的传播将由高影响力的科学期刊，会议演讲和YouTube讲座视频中的出版物完成。该项目的智力优点在于了解基于集成的Sttram和SD的STTRAM设备与SD的集成兼容性，并开发了高度可扩展的3D横杆阵列。将通过执行以下具体目的来实现目标：（i）建模和模拟Sttram-SD阵列，（ii）弹性分析和优化研究，以最大程度地降低设备级别变化对性能度量的影响，（iii）优化Sttram-SD架构对高性能计算和IV型（IV）的设计，（iv频带工程和掺杂工程过渡金属氧化物和电极堆栈，（v）设计和制造小型Sttram-SD阵列，电气测试和建模对基准模拟以及实验结果。预计该项目的成功完成将导致对Sttram与SD兼容性的基本了解，并提供平台技术来发展高密度的记忆，这将对商业化和推进未来主义应用程序产生变革性的影响。

项目成果

Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V

• DOI: 10.1109/tcad.2020.2984407
• 发表时间: 2020-12
• 期刊: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• 影响因子: 2.9
• 作者: Asmit De;Aditya Basu;Swaroop Ghosh;T. Jaeger

Test challenges and solutions for emerging non-volatile memories

新兴非易失性存储器的测试挑战和解决方案

• DOI: 10.1109/vts.2018.8368632
• 发表时间: 2018
• 期刊: VLSI Test Symposium (VTS
• 作者: Khan, Mohammad Nasim;Ghosh, Swaroop
• 通讯作者: Ghosh, Swaroop

Power side channel attack analysis and detection

电源侧通道攻击分析与检测

• 发表时间: 2020
• 期刊: international conference on computer-aided design
• 作者: Gattu, Navyata and

Dynamic Computing in Memory (DCIM) in Resistive Crossbar Arrays

电阻交叉阵列中的内存动态计算 (DCIM)

• DOI: 10.1109/iccd.2018.00036
• 发表时间: 2018
• 期刊: IEEE 36th International Conference on Computer Design (ICCD
• 作者: Motaman, Seyedhamidreza;Ghosh, Swaroop
• 通讯作者: Ghosh, Swaroop

Information Leakage Attacks on Emerging Non-Volatile Memory and Countermeasures

新兴非易失性存储器的信息泄露攻击及对策

• DOI: 10.1145/3218603.3218649
• 发表时间: 2018
• 期刊: International Symposium on Low Power Electronics and Design
• 作者: Khan, Mohammad Nasim;Ghosh, Swaroop
• 通讯作者: Ghosh, Swaroop