Study on Nanometer SOI Device Structure

SOI上SiGe埋沟MOSTFT的有效空穴迁移率取决于SiGe沟道结构和晶体质量。本工作采用低压CVD法在SIMOX衬底上于550℃形成了单量子阱（SQW）和三量子威尔斯（TQW）两种埋沟结构。该生长装置是基于超净技术建造的。合金的Ge组成为0.2。SQW的SiGe阱宽度Lz为13 nm，TQW的固定为3 nm。对于TQW，Si势垒厚度LB为2和8 nm。在该层上制作了具有5.9nm栅氧化层的MOSFET。在室温下获得了两种器件类型的有效空穴迁移率μeff与有效电场Eeff的关系。与SQW器件相比，TQW器件的迁移率提高了近60%。迁移率的提高可能是由于具有高空穴迁移率的SiGe量子威尔斯中捕获的空穴数量的增加。在40 nm厚的SOI上制作的SiGe阱宽为3 nm、Si势垒厚度为2 nm的三量子威尔斯阱沟道器件获得了最佳的有效空穴迁移率。结果表明，SOI上的多量子威尔斯沟道pMOSFET提高了有效空穴迁移率，改善了器件性能。

The effective hole mobility of SiGe buried-channel MOSTFT on SOI depends on the SiGe channel structure as well as the crystalline quality. In this work, the two sorts of buried-channel structure that consisted of single quantum well (SQW) and triple quantum wells (TQW) were formed at 550℃ on SIMOX wafers by low-pressure CVD. The growth apparatus was built on the basis of ultra-clean technology. The Ge composition of the alloy was 0.2. The SiGe well width, Lz, was 13 nm for SQW and fixed at 3 nm for TQW. The Si barrier thickness, LB, was 2 and 8 nm for TQW. The MOSFETs with the 5.9 nm gate oxide were fabricated on the layers. The Effective hole mobility, μeff, versus effective electric field, Eeff, for the both device types were obtained at room temperature. The mobility of TQW devices was enhanced nearly by 60 %, compared with that for the SQW devices. The mobility enhancement might be due to the increase of the number of holes trapped in the SiGe quantum wells that had the high hole mobility. The best effective hole mobility was obtained for the triple quantum wells channel device with the 3-nm SiGe well width and 2-nm Si barrier thickness fabricated on 40-nm-thick SOI. It was concluded that the multiple quantum wells channel pMOSFETs on SOI enhanced the effective hole mobility and promoted the device performance.