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VLSI-Based Robot Electronics System

基于 VLSI 的机器人电子系统

基本信息

批准号：
63550297
负责人：
KAMEYAMA Michitaka
金额：
$ 1.41万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (C)
财政年份：
1988
资助国家：
日本
起止时间：
1988 至 1989
项目状态：
已结题

项目摘要

In robot applications, it is necessary to respond immediately to the change of environment and to move according to the recognized results. A series of chains consisting of many kinds of processing is required between the environment recognition and the movement. In this case, it is necessary to minimize the absolute delay time in each processing module, so that the reduction of latency is very important in the design of VLSI processors for robotics. This research is dedicated for the above purpose, and the main results obtained are summarized as follows:1.Effective Hardware Algorithm To minimize the absolute delay time an algorithm with less computational complexity is desirable. A typical example is the coordinate transformation processor that has been implemented with CMOS LSI. Two-dimensional coordinate rotation is effectively used as a basic operation, which makes the processing speed about 20 times faster than the conventional approach.2.Highly Parallel architecture The use of parallelism is another effective approach to reduce the delay time. In the proposed architecture, the parallel processing elements oT subprocessors are connected through an interconnection network so that each data output is transferred immediately with minimum latency. The applications are also considered such as a matrix operation processor for digital servoing, an inverse dynamics processor, an image recognition processor based on chain-code matching and an obstacle avoidance processor.3.Neural Network for Optimum Solution Discrete-time neural network for highly parallel hardware is proposed. The function of each cell is a multiply-add operation, so that optimum solutions are always obtained for the optimization problems such as the minimization of an evaluation function.

在机器人应用中，需要对环境的变化立即做出响应，并根据识别结果进行运动。环境识别与运动之间需要一系列由多种处理组成的链条。在这种情况下，有必要最小化每个处理模块中的绝对延迟时间，因此延迟的减少在用于机器人的VLSI处理器的设计中非常重要。本文的主要研究内容如下：1.有效的硬件算法为了使绝对延迟时间最小化，需要一种计算复杂度较小的算法。一个典型的例子是已经用CMOS LSI实现的坐标变换处理器。二维坐标旋转被有效地用作基本操作，这使得处理速度比常规方法快约20倍。2.高度并行架构并行性的使用是另一种有效的减少延迟时间的方法。在所提出的结构中，并行处理元件oT子处理器通过互连网络连接，使每个数据输出被立即传输，以最小的延迟。应用也被认为是如矩阵运算处理器的数字伺服，逆动力学处理器，图像识别处理器的基础上链码匹配和避障处理器。3.神经网络的最佳解决方案离散时间神经网络的高度并行硬件提出。每个单元的函数是乘加运算，使得对于诸如评价函数的最小化的优化问题总是获得最优解。