Performance Optimization of VLSI Interconnect

互连正在迅速成为影响集成电路行为的最重要因素之一。这个项目解决了开发下一代计算机辅助设计工具来处理这些问题的问题。这项工作的目的是应用互连快速模拟的最新进展来解决互连设计中的优化问题。具体地说，正在调查与电源母线、时钟网络和信号网的设计有关的问题。在供应网络的情况下，正在考虑在性能和分析简易性之间提供良好折衷的结构化网状拓扑结构。在信号网络的情况下，研究了在具有阻性、电容和电感效应的环境下，考虑与详细布线的相互作用，构造最优直线塞纳树的问题。除了延迟，这项工作还考虑了优化过程中的信号完整性和可制造性。

Interconnect is rapidly becoming one of the most important factors in influencing the behavior of integrated circuits. This project addresses the problem of developing next- generation computer-aided design tools to handle these problems. The objective of this work is to apply recent advances in fast simulation of interconnect to solve optimization problems in interconnect design. Specifically, problems related to the design of supply busses, clock networks and signal nets are being investigated. In case of supply nets, structured mesh topologies that provide a good tradeoff between performance and ease of analysis are being considered. In case of signal nets, the problem of building optimal rectilinear Seiner trees under an environment of resistive, capacitive and inductive effects are being studied, with consideration to the interactions with detailed routing. In addition to delay, the work incorporates considerations of signal integrity and manufacturability during the optimization.