CPA: Closing the Gap in VLSI Physical Design

提案编号：0430077机构：加州大学洛杉矶分校校长：丛，杰森标题：注册会计师：缩小差距在超大规模集成电路的物理设计摘要：戈登摩尔的著名观察，每个集成电路的晶体管的数量每两年翻一番，在过去的四十年里一直是正确的。这种爆炸性增长的影响已经改变了社会的几乎所有领域，使最近的所有信息技术革命成为可能：个人计算、电信、生物信息学、数字成像、电子商务等。随着硅基电路密度持续增加的最终经济和物理障碍开始形成，自动化设计工具在确定系统性能方面起着越来越重要的作用。 最近的研究表明，现有的电路布局工具是令人惊讶的远离最佳（70-150%的线长过剩）的简化电路基准改编自真实的工业测试案例。 如果能够弥补这一质量差距，所产生的效益将相当于制造工艺技术的几代进步，在可行的情况下，其成本通常以数十亿美元计。 本研究的目标是开发新的，可扩展的算法的超大规模集成电路的物理设计，使多个摩尔定律代的性能改善，通过3-D设计优化在复杂的时序和温度的约束。 在这个项目中的重点将主要放在电路布局，因为它是最约束的互连布线，主导系统性能的布局的步骤。 核心布局问题是在一个给定的矩形内安排所有的电路元件，使得它们中没有两个重叠，并且使得总线长的标准估计最小化。 对现有算法偏离最优性以及这种偏离如何随着设计尺寸的增加而变化的更广泛和更深入的分析将用于开发用于核心布局模型问题的高效和优化的布局引擎。 该引擎的可扩展性将来自多尺度框架，其中目标和约束同时表示和操纵跨分辨率尺度的层次结构。 然后，该引擎将被增强以处理2-D和3-D设置中的各种复杂约束，例如，信号传播时间、最大布线密度、最高温度以及尺寸变化很大的电路元件。以几乎可以忽略不计的成本推进整个一代技术的等效物的更广泛影响将是相当大的。原始计算能力的大幅提升最终转化为新的定性理解，因为以前难以解决的问题逐渐变得可以解决。此外，潜在的更大影响是，通过将详细的物理建模纳入可扩展的程序中，以优化数百万个相互连接的元素，可能会在基础科学方面取得进展。 最终，纳米级设计问题的巨大规模和复杂性只能通过尚未开发的可扩展算法来实现。 一个真正的可扩展的物理现实的VLSI设计方法的成功制定可以预期对未来的设计范式具有持久和深远的影响。

PROPOSAL NO: 0430077INSTITUTION: University of California-Los AngelesPRINCIPAL INVESTIGATOR: Cong, JasonTITLE: CPA: Closing the Gap in VLSI Physical DesignAbstract:Gordon Moore's famous observation that the number of transistors per integrated circuit doubles every two years has held true for the last four decades. The impact of this explosive increase has already transformed practically all areas of society, making possible all the recent revolutions in information technology: personal computing, telecommunications, bioinformatics, digital imaging, electronic commerce, etc. As the final economic and physical barriers to continued increases in silicon-based circuit densities begin to take shape, automated design tools play an ever more important role in determining system performance. Recent studies showed that existing circuit-placement tools are surprisingly far from optimal (70-150% excess wirelength) on simplified circuit benchmarks adapted from real industrial test cases. If this quality gap can be closed, the resulting benefit will be equivalent to advancing several generations in fabrication process technology, the cost of which, when feasible, is normally measured in billions of US dollars. The goal of this research is to develop new, scalable algorithms for VLSI physical design to enable multiple Moore's-Law generations of performance improvement through 3-D design optimization in the presence of complex timing and temperature constraints. The focus in this project will be primarily on circuit placement, as it is the step that most constrains the layout of the interconnect wiring which dominates system performance. The core placement problem is to arrange all circuit elements within a given rectangle such that no two of them overlap and such that a standard estimate of total wirelength is minimized. A broader and deeper analysis of existing algorithms' deviation from optimality and how that deviation changes as design sizes increase will be used to develop a highly efficient and optimized placement engine for the core placement model problem. Scalability of the engine will derive from a multiscale framework, in which objectives and constraints are simultaneously represented and manipulated across a hierarchy of resolution scales. This engine will then be and augmented to handle various complex constraints in both the 2-D and 3-D settings, e.g., signal propagation times, maximum wiring density, maximum temperature, and circuit elements of widely varying sizes.The broader impact of advancing the equivalent of an entire technology generation at almost negligible cost would be considerable. A large jump in raw computing power ultimately translates into new qualitative understanding, as previously intractable problems gradually become solvable. Of potentially even greater impact, moreover, are the possible advances in basic science to be obtained by incorporating detailed physical modeling into a scalable program for optimization over millions of interconnected elements. Ultimately, the vast size and complexity of nanoscale design problems can realistically be approached only by scalable algorithms yet to be developed. The successful formulation of a truly scalable methodology for physically realistic VLSI designs can be expected to have lasting and far-reaching impact on future design paradigms.